- 专利标题： Via-in-via structure for high density package integrated inductor
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申请号： US16635147申请日： 2017-09-28
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公开(公告)号： US11676950B2公开(公告)日： 2023-06-13
- 发明人: Krishna Bharath , Sriram Srinivasan , Amruthavalli Alur , Kaladhar Radhakrishnan , Huong Do , William Lambert
- 申请人： INTEL CORPORATION
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Essential Patents Group, LLP
- 国际申请： PCT/US2017/054098 2017.09.28
- 国际公布： WO2019/066868A 2019.04.04
- 进入国家日期： 2020-01-29
- 主分类号： H01L23/498
- IPC分类号： H01L23/498 ; H01L23/64 ; H01L25/065 ; H01L25/16
摘要：
An apparatus is provided which comprises: a plurality of plated through holes; a material with magnetic properties adjacent to the plurality of plated through holes; and one or more conductors orthogonal to a length of the plurality of plated through holes, the one or more conductors to couple one plated through hole of the plurality with another plated through hole of the plurality such that an inductor is formed.
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