公开(公告)号：US20240063202A1

公开(公告)日：2024-02-22

申请号：US17820968

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Thomas Sounart ,  Henning Braunisch ,  William J. Lambert ,  Kaladhar Radhakrishnan ,  Shawna M. Liff ,  Mohammad Enamul Kabir ,  Omkar G. Karhade ,  Kimin Jun ,  Johanna M. Swan

IPC: H01L25/18 ,  H01L23/522 ,  H01L49/02 ,  H01L23/00 ,  H01L23/498 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L23/5223 ,  H01L28/90 ,  H01L24/08 ,  H01L23/49811 ,  H01L23/481 ,  H01L25/50 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of IC dies in a dielectric material, adjacent layers in the plurality of layers being coupled together by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; a package substrate coupled to a first side of the plurality of layers by second interconnects; a support structure coupled to a second side of the plurality of layers by third interconnects, the second side being opposite to the first side; and capacitors in at least the plurality of layers or the support structure. The capacitors are selected from at least planar capacitors, deep trench capacitors and via capacitors.

公开(公告)号：US11830809B2

公开(公告)日：2023-11-28

申请号：US16829336

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Ying Wang ,  Yikang Deng ,  Junnan Zhao ,  Andrew James Brown ,  Cheng Xu ,  Kaladhar Radhakrishnan

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228 ,  H01L28/10

Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a magnetic structure around the conductive line, and material stubs at side faces of the magnetic structure.

公开(公告)号：US20230096368A1

公开(公告)日：2023-03-30

申请号：US17485243

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel Elsherbini ,  Johanna Swan ,  Feras Eid ,  Thomas L. Sounart ,  Henning Braunisch ,  Beomseok Choi ,  Krishna Bharath ,  Kaladhar Radhakrishnan ,  William J. Lambert

IPC: H01L49/02 ,  H01F27/255 ,  H01F27/28 ,  H01F41/04 ,  H01F41/02 ,  H01L23/498 ,  H01L23/64 ,  H01L21/48

Abstract: An inductor structure, a package substrate, an integrated circuit device, an integrated circuit device assembly and a method of fabricating the inductor structure. The inductor structure includes: an electrically conductive body; and a magnetic structure including a non-electrically-conductive magnetic material, wherein: one of the magnetic structure or the electrically conductive body wraps around another one of the magnetic structure or the electrically conductive body to form the inductor structure therewith; and at least one of the electrically conductive body or the magnetic structure has a granular microstructure including randomly distributed particles presenting substantially non-linear particle-to-particle boundaries with one another.

公开(公告)号：US20230095063A1

公开(公告)日：2023-03-30

申请号：US17484286

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Beomseok Choi ,  William J. Lambert ,  Krishna Bharath ,  Kaladhar Radhakrishnan ,  Adel Elsherbini ,  Henning Braunisch ,  Stephen Morein ,  Aleksandar Aleksov ,  Feras Eid

IPC: G05F1/44 ,  H01L23/50 ,  H01L25/065

Abstract: In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

公开(公告)号：US20220310512A1

公开(公告)日：2022-09-29

申请号：US17839337

申请日：2022-06-13

Applicant: INTEL CORPORATION

Inventor： Huong Do ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Yikang Deng ,  Amruthavalli P. Alur

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/66 ,  H01L21/768

Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.

公开(公告)号：US11335616B2

公开(公告)日：2022-05-17

申请号：US16498775

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Malavarayan Sankarasubramanian ,  Yongki Min ,  Ashay A. Dani ,  Kaladhar Radhakrishnan

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/522

Abstract: A semiconductor package may include a composite magnetic inductor that is formed integral with the semiconductor substrate. The composite magnetic inductor may include a composite magnetic resin layer and a plurality of conductive layers arranged such that the composite magnetic resin layer is interleaved between successive conductive layers. The resultant composite magnetic inductor may be disposed between dielectric layers. A core layer may be disposed proximate the composite magnetic inductor. A build-up layer may be disposed proximate the core layer or proximate the composite magnetic inductor in a coreless semiconductor substrate. A semiconductor die may couple to the build-up layer. The composite magnetic inductor beneficially provides a greater inductance than external inductors coupled to the semiconductor package.

公开(公告)号：US10950555B2

公开(公告)日：2021-03-16

申请号：US16481031

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Kaladhar Radhakrishnan ,  Jaejin Lee ,  Hao-Han Hsu ,  Chung-Hao J. Chen ,  Dong-Ho Han

IPC: H01L23/66 ,  H01L23/552 ,  H01L21/48 ,  H01L23/498 ,  H01L25/18 ,  H05K1/18 ,  H01L23/64 ,  H01L49/02

Abstract: Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer, a conductive layer formed in the foundation layer, and a magnetic layer formed between the conductive and the foundation layer. The conductive layer and the magnetic layer are coupled to form a low-profile inductor shield. The semiconductor package also has a dielectric layer formed between the magnetic and foundation layer. The foundation layer is mounted between a motherboard and a semiconductor die, where the foundation layer is attached to the motherboard with solder balls. Accordingly, the low-profile inductor shield may include a z-height that is less than a z-height of the solder balls. The low-profile inductor shield may have solder pads that are coupled to the conductive layer. The foundation layer may include at least one of voltage regulator and inductor, where the inductor is located above the low-profile inductor shield.

公开(公告)号：US10748842B2

公开(公告)日：2020-08-18

申请号：US15926531

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kaladhar Radhakrishnan ,  Kemal Aygun

IPC: H01L23/49 ,  H01L23/498 ,  H01L21/68 ,  H01L21/48 ,  H01L23/00

Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

公开(公告)号：US12074514B2

公开(公告)日：2024-08-27

申请号：US17025745

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Kaladhar Radhakrishnan ,  Beomseok Choi ,  Michael Hill

IPC: H02M3/07 ,  H01L23/00 ,  H01L25/065 ,  H02M1/00

CPC classification number: H02M3/07 ,  H01L24/17 ,  H01L25/0655 ,  H01L2924/1427 ,  H02M1/0045 ,  H02M1/009

Abstract: Embodiments disclosed herein include two stage voltage regulators for electronic systems. In an embodiment, a voltage regulator comprises a switched capacitor voltage regulator (SCVR). In an embodiment, the SCVR receives a first voltage as an input and outputs a plurality of SCVR output voltages. In an embodiment, the voltage regulator further comprises a low-dropout (LDO) regulator. In an embodiment, the LDO regulator receives one or more of the plurality of SCVR output voltages as LDO input voltages, and where the LDO regulator outputs a second voltage.

公开(公告)号：US11916006B2

公开(公告)日：2024-02-27

申请号：US17822200

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L23/498 ,  G05F1/46 ,  H01L23/00 ,  H01L23/522 ,  H01L23/64 ,  H01L49/02 ,  H01F27/24

CPC classification number: H01L23/49838 ,  G05F1/46 ,  H01L23/5226 ,  H01L23/642 ,  H01L23/645 ,  H01L24/17 ,  H01L28/10 ,  H01L28/40 ,  H01F27/24

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.