公开(公告)号：US11430724B2

公开(公告)日：2022-08-30

申请号：US16646529

申请日：2017-12-30

申请人： Intel Corporation

发明人： Debendra Mallik ,  Robert L. Sankman ,  Robert Nickerson ,  Mitul Modi ,  Sanka Ganesan ,  Rajasekaran Swaminathan ,  Omkar Karhade ,  Shawna M. Liff ,  Amruthavalli Alur ,  Sri Chaitra J. Chavali

IPC分类号： H01L23/52 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

摘要： Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US11676950B2

公开(公告)日：2023-06-13

申请号：US16635147

申请日：2017-09-28

申请人： INTEL CORPORATION

发明人： Krishna Bharath ,  Sriram Srinivasan ,  Amruthavalli Alur ,  Kaladhar Radhakrishnan ,  Huong Do ,  William Lambert

IPC分类号： H01L23/498 ,  H01L23/64 ,  H01L25/065 ,  H01L25/16

CPC分类号： H01L25/16 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/642 ,  H01L23/645

摘要： An apparatus is provided which comprises: a plurality of plated through holes; a material with magnetic properties adjacent to the plurality of plated through holes; and one or more conductors orthogonal to a length of the plurality of plated through holes, the one or more conductors to couple one plated through hole of the plurality with another plated through hole of the plurality such that an inductor is formed.

公开(公告)号：US20210098436A1

公开(公告)日：2021-04-01

申请号：US16635147

申请日：2017-09-28

申请人： INTEL CORPORATION

发明人： Krishna Bharath ,  Sriram Srinivasan ,  Amruthavalli Alur ,  Kaladhar Radhakrishnan ,  Huong Do ,  William Lambert

IPC分类号： H01L25/16 ,  H01L23/498 ,  H01L23/64

摘要： An apparatus is provided which comprises: a plurality of plated through holes; a material with magnetic properties adjacent to the plurality of plated through holes; and one or more conductors orthogonal to a length of the plurality of plated through holes, the one or more conductors to couple one plated through hole of the plurality with another plated through hole of the plurality such that an inductor is formed.

公开(公告)号：US11508636B2

公开(公告)日：2022-11-22

申请号：US16024697

申请日：2018-06-29

申请人： Intel Corporation

发明人： Andrew Brown ,  Ji Yong Park ,  Siddharth Alur ,  Cheng Xu ,  Amruthavalli Alur

IPC分类号： H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

摘要： Embodiments include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a substrate, and a plurality of conductive features formed over the substrate. In an embodiment, a bilayer build-up layer is formed over the plurality of conductive features. In an embodiment, the bilayer build-up layer comprises a first dielectric layer and a second dielectric layer. In an embodiment, a surface of the first dielectric layer comprises depressions. In an embodiment, the second dielectric layer is disposed in the depressions of the surface of the first dielectric layer.

公开(公告)号：US20200066830A1

公开(公告)日：2020-02-27

申请号：US16107778

申请日：2018-08-21

申请人： Intel Corporation

发明人： Krishna Bharath ,  Wei-Lun Jen ,  Huong Do ,  Amruthavalli Alur

IPC分类号： H01L49/02 ,  H01L23/522 ,  H01L23/64 ,  H01F27/26 ,  H01L23/00

摘要： A microelectronics package comprises a substrate comprising at least two conductive layers that are separated by a first dielectric. At least one island comprising a magnetic material is embedded within the dielectric between the two conductive layers. An inductor structure extends within a via in the at least one island. The via extends between the two conductive layers. The inductor structure comprises a conductive wall along a sidewall of the via, and wherein the conductive wall surrounds a second dielectric and is electrically coupled to the two conductive layers.