Invention Grant
- Patent Title: Hard mask layer below via structure in display device
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Application No.: US16871257Application Date: 2020-05-11
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Publication No.: US11682692B2Publication Date: 2023-06-20
- Inventor: Chia-Hua Lin , Hsun-Chung Kuang , Yu-Hsing Chang , Yao-Wen Chang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L27/15
- IPC: H01L27/15 ; H01L33/60 ; H01L33/40 ; H01L33/62

Abstract:
In some embodiments, the present disclosure relates to a display device that includes a reflector electrode coupled to an interconnect structure. An isolation structure is disposed over the reflector electrode, and a transparent electrode is disposed over the isolation structure. Further, an optical emitter structure is disposed over the transparent electrode. A via structure extends from a top surface of the isolation structure to the reflector electrode and comprises an outer portion that directly overlies the top surface of the isolation structure. A hard mask layer is arranged directly between the top surface of the isolation structure and the outer portion of the via structure.
Public/Granted literature
- US20210265417A1 HARD MASK LAYER BELOW VIA STRUCTURE IN DISPLAY DEVICE Public/Granted day:2021-08-26
Information query
IPC分类: