Invention Grant
- Patent Title: Inner spacer features for multi-gate transistors
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Application No.: US17706296Application Date: 2022-03-28
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Publication No.: US11682714B2Publication Date: 2023-06-20
- Inventor: Bone-Fong Wu , Chih-Hao Yu , Chia-Pin Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/06 ; H01L29/423 ; H01L29/78 ; H01L21/02

Abstract:
A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.
Public/Granted literature
- US20220223718A1 Inner Spacer Features for Multi-Gate Transistors Public/Granted day:2022-07-14
Information query
IPC分类: