公开(公告)号：US20250164690A1

公开(公告)日：2025-05-22

申请号：US18593331

申请日：2024-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Yu-Hao Kuo ,  Chih-Hao Yu ,  Ren-Fen Tsui ,  Jui Lin Chao ,  Hsing-Kuo Hsia ,  Kuo-Chung Yee ,  Chen-Hua Yu

IPC: G02B6/122 ,  G02B6/12 ,  G02B6/13

Abstract: Optical devices and methods of manufacture are presented in which metallization layers are formed over a first active layer of first optical components, a first opening is formed through the metallization layers, a first semiconductor die is bonded over the metallization layers, and a laser die is bonded over the metallization layers, wherein after the bonding the laser die a first mirror located within the laser die is aligned with a second mirror through the first opening.

公开(公告)号：US11682714B2

公开(公告)日：2023-06-20

申请号：US17706296

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bone-Fong Wu ,  Chih-Hao Yu ,  Chia-Pin Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/66553 ,  H01L29/0653 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/7853 ,  H01L21/0214 ,  H01L21/0228

Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.

公开(公告)号：US20230187288A1

公开(公告)日：2023-06-15

申请号：US18165007

申请日：2023-02-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jhih Syu ,  Chih-Hao Yu ,  Chang-Yun Chang ,  Hsiu-Hao Tsao ,  Yu-Jiun Peng

IPC: H01L21/66 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L22/20 ,  H01L21/823431 ,  H01L21/823456 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes forming an active region on a substrate, forming a sacrificial gate stack engaging the active region, measuring a gate length of the sacrificial gate stack at a height lower than a top surface of the active region, selecting an etching recipe based on the measured gate length of the sacrificial gate stack, etching the sacrificial gate stack with the etching recipe to form a gate trench, and forming a metal gate stack in the gate trench.

公开(公告)号：US20210249271A1

公开(公告)日：2021-08-12

申请号：US16787229

申请日：2020-02-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jiun Peng ,  Hsiu-Hao Tsao ,  Shu-Han Chen ,  Chang-Jhih Syu ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Chih-Hao Yu ,  Chang-Yun Chang

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L29/45 ,  H01L21/285 ,  H01L21/3115 ,  H01L21/311 ,  H01L29/66

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

公开(公告)号：US09954076B2

公开(公告)日：2018-04-24

申请号：US15486549

申请日：2017-04-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hao Yu ,  Sheng-chen Wang ,  Sai-Hooi Yeong

IPC: H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66795

Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. A width of the separation plug in a second direction perpendicular to the first direction is smaller than a width of the first gate structure in the second direction, when viewed in plan view.

公开(公告)号：US12198988B2

公开(公告)日：2025-01-14

申请号：US18165007

申请日：2023-02-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jhih Syu ,  Chih-Hao Yu ,  Chang-Yun Chang ,  Hsiu-Hao Tsao ,  Yu-Jiun Peng

IPC: H01L21/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66

Abstract: A method includes forming an active region on a substrate, forming a sacrificial gate stack engaging the active region, measuring a gate length of the sacrificial gate stack at a height lower than a top surface of the active region, selecting an etching recipe based on the measured gate length of the sacrificial gate stack, etching the sacrificial gate stack with the etching recipe to form a gate trench, and forming a metal gate stack in the gate trench.

公开(公告)号：US20240379822A1

公开(公告)日：2024-11-14

申请号：US18780150

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bone-Fong Wu ,  Chih-Hao Yu ,  Chia-Pin Lin

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.

公开(公告)号：US11574846B2

公开(公告)日：2023-02-07

申请号：US17075313

申请日：2020-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jhih Syu ,  Chih-Hao Yu ,  Chang-Yun Chang ,  Hsiu-Hao Tsao ,  Yu-Jiun Peng

IPC: H01L21/66 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

Abstract: A method of controlling gate formation of a semiconductor device includes acquiring a correlation between gate critical dimensions (CDs) and etching recipes for forming gate trenches; measuring a gate CD on a target wafer; determining an etching recipe based on the correction and the measured gate CD; and performing an etching process on the target wafer to form a gate trench with the determined etching recipe.

公开(公告)号：US20210336034A1

公开(公告)日：2021-10-28

申请号：US16937164

申请日：2020-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bone-Fong Wu ,  Chih-Hao Yu ,  Chia-Pin Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.

公开(公告)号：US09659930B1

公开(公告)日：2017-05-23

申请号：US14932383

申请日：2015-11-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hao Yu ,  Sheng-chen Wang ,  Sai-Hooi Yeong

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/66545 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66795

Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. A width of the separation plug in a second direction perpendicular to the first direction is smaller than a width of the first gate structure in the second direction, when viewed in plan view.