Invention Grant
- Patent Title: Multi-dimensional data path architecture
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Application No.: US17334960Application Date: 2021-05-31
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Publication No.: US11693796B2Publication Date: 2023-07-04
- Inventor: Paul Nicholas Whatmough , Zhi-Gang Liu , Supreet Jeloka , Saurabh Pijuskumar Sinha , Matthew Mattina
- Applicant: Arm Limited
- Applicant Address: GB Cambridge
- Assignee: Arm Limited
- Current Assignee: Arm Limited
- Current Assignee Address: GB Cambridge
- Agency: Pramudji Law Group PLLC
- Agent Ari Pramudji
- Main IPC: G06F13/16
- IPC: G06F13/16 ; G06F13/40 ; G06N3/063 ; G06F7/544 ; G06F15/80

Abstract:
Various implementations described herein are directed to a device having a multi-layered logic structure with a first logic layer and a second logic layer arranged vertically in a stacked configuration. The device may have a memory array that provides data, and also, the device may have an inter-layer data bus that vertically couples the memory array to the multi-layered logic structure. The inter-layer data bus may provide multiple data paths to the first logic layer and the second logic layer for reuse of the data provided by the memory array.
Public/Granted literature
- US20220382690A1 Multi-Dimensional Data Path Architecture Public/Granted day:2022-12-01
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