Invention Grant
- Patent Title: Passivation layers for semiconductor devices
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Application No.: US16807305Application Date: 2020-03-03
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Publication No.: US11695055B2Publication Date: 2023-07-04
- Inventor: Cheng-Yi Peng , Ching-Hua Lee , Song-Bor Lee
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L29/78 ; H01L29/06 ; H01L27/092 ; H01L29/66 ; H01L21/8238 ; H01L29/423 ; H01L29/786 ; H01L29/775

Abstract:
The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers. A first portion of the passivation layer is disposed between the epitaxial region and the stack of first and second semiconductor layers and a second portion of the passivation layer is disposed on sidewalls of the nanostructured channel regions.
Public/Granted literature
- US20210280486A1 PASSIVATION LAYERS FOR SEMICONDUCTOR DEVICES Public/Granted day:2021-09-09
Information query
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