公开(公告)号：US12288809B2

公开(公告)日：2025-04-29

申请号：US18612701

申请日：2024-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Miao-Syuan Fan ,  Pei-Wei Lee ,  Ching-Hua Lee ,  Jung-Wei Lee

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure relates to a semiconductor device includes first and second source/drain (S/D) regions doped with lead (Pb) at a first dopant concentration. The semiconductor device also includes a channel region between the first and second S/D regions, where the channel region is doped with Pb at a second dopant concentration that is lower than the first dopant concentration. The semiconductor device further includes first and second S/D contacts in contact with the first and second S/D regions, respectively. The semiconductor device also includes a gate electrode over the channel region.

公开(公告)号：US11929422B2

公开(公告)日：2024-03-12

申请号：US17876816

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi Peng ,  Ching-Hua Lee ,  Song-Bor Lee

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66439 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/78696

Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers. A first portion of the passivation layer is disposed between the epitaxial region and the stack of first and second semiconductor layers and a second portion of the passivation layer is disposed on sidewalk of the nanostructured channel regions

公开(公告)号：US10276444B2

公开(公告)日：2019-04-30

申请号：US15724650

申请日：2017-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hua Lee ,  Jung-Wei Lee ,  Wen-Chieh Huang

IPC: H01L21/8234 ,  H01L21/285 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02

Abstract: A method for forming a fin-based transistor includes forming a fin on a substrate; overlaying at least an upper portion of the fin with nitrogen-based radicals, wherein the nitrogen-based radicals are distributed along a sidewall and over a top surface of the upper portion of the fin with respective different concentrations; and forming an oxide layer over the upper portion of the fin using a thermal oxidation process.

公开(公告)号：US11251268B2

公开(公告)日：2022-02-15

申请号：US16937365

申请日：2020-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Miao-Syuan Fan ,  Pei-Wei Lee ,  Ching-Hua Lee ,  Jung-Wei Lee

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/10 ,  H01L29/40

Abstract: The present disclosure relates to a semiconductor device includes first and second source/drain (S/D) regions doped with lead (Pb) at a first dopant concentration. The semiconductor device also includes a channel region between the first and second S/D regions, where the channel region is doped with Pb at a second dopant concentration that is lower than the first dopant concentration. The semiconductor device further includes first and second S/D contacts in contact with the first and second S/D regions, respectively. The semiconductor device also includes a gate electrode over the channel region.

公开(公告)号：US11990512B2

公开(公告)日：2024-05-21

申请号：US17650867

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Miao-Syuan Fan ,  Pei-Wei Lee ,  Ching-Hua Lee ,  Jung-Wei Lee

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a semiconductor device includes first and second source/drain (S/D) regions doped with lead (Pb) at a first dopant concentration. The semiconductor device also includes a channel region between the first and second S/D regions, where the channel region is doped with Pb at a second dopant concentration that is lower than the first dopant concentration. The semiconductor device further includes first and second S/D contacts in contact with the first and second S/D regions, respectively. The semiconductor device also includes a gate electrode over the channel region.

公开(公告)号：US11695055B2

公开(公告)日：2023-07-04

申请号：US16807305

申请日：2020-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi Peng ,  Ching-Hua Lee ,  Song-Bor Lee

IPC: H01L23/31 ,  H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775

CPC classification number: H01L29/66439 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/78696

Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers. A first portion of the passivation layer is disposed between the epitaxial region and the stack of first and second semiconductor layers and a second portion of the passivation layer is disposed on sidewalls of the nanostructured channel regions.

公开(公告)号：US11232953B2

公开(公告)日：2022-01-25

申请号：US16573596

申请日：2019-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Miao-Syuan Fan ,  Ching-Hua Lee ,  Ming-Te Chen ,  Jung-Wei Lee ,  Pei-Wei Lee

IPC: H01L21/285 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device includes a gate structure disposed over a channel region, a source/drain epitaxial layer disposed at a source/drain region, a nitrogen containing layer disposed on the source/drain epitaxial layer, a silicide layer disposed on the nitrogen containing layer, and a conductive contact disposed on the silicide layer.