- Patent Title: Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding, and related methods and devices
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Application No.: US17365741Application Date: 2021-07-01
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Publication No.: US11705432B2Publication Date: 2023-07-18
- Inventor: Hiroki Fujisawa , Raj K. Bansal , Shunji Kuwahara , Mitsuaki Katagiri , Satoshi Isa
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- The original application number of the division: US16553549 2019.08.28
- Main IPC: G11C5/04
- IPC: G11C5/04 ; H01L25/065 ; H01L25/00 ; H01L23/00 ; G11C11/4096 ; H01L25/18

Abstract:
Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.
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