公开(公告)号：US20190304955A1

公开(公告)日：2019-10-03

申请号：US16447749

申请日：2019-06-20

Applicant: Micron Technology, Inc.

Inventor： Dai Sasaki ,  Mitsuaki Katagiri ,  Satoshi Isa

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/00 ,  H01L21/66

Abstract: Some embodiments include an apparatus having a first chip and a second chip. Each of the first and second chips comprises a multilevel wiring structure and a redistribution wiring layer over the multilevel wiring structure. The redistribution wiring layers include redistribution wiring and pads electrically coupled to the redistribution wiring. The first chip is mounted above the second chip so that the redistribution wiring layer of the first chip faces the redistribution wiring layer of the second chip. The pad of the first chip faces the pad of the second chip, and is vertically spaced from the pad of the second chip by an intervening insulative region. The redistribution wiring of the second chip is electrically coupled to the redistribution wiring of the first chip through a bonding region.

公开(公告)号：US10431566B2

公开(公告)日：2019-10-01

申请号：US16056250

申请日：2018-08-06

Applicant: Micron Technology, Inc.

Inventor： Dai Sasaki ,  Mitsuaki Katagiri ,  Satoshi Isa

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/00 ,  H01L21/66 ,  H01L23/525

Abstract: Some embodiments include an apparatus having a first chip and a second chip. Each of the first and second chips comprises a multilevel wiring structure and a redistribution wiring layer over the multilevel wiring structure. The redistribution wiring layers include redistribution wiring and pads electrically coupled to the redistribution wiring. The first chip is mounted above the second chip so that the redistribution wiring layer of the first chip faces the redistribution wiring layer of the second chip. The pad of the first chip faces the pad of the second chip, and is vertically spaced from the pad of the second chip by an intervening insulative region. The redistribution wiring of the second chip is electrically coupled to the redistribution wiring of the first chip through a bonding region.

公开(公告)号：US11081468B2

公开(公告)日：2021-08-03

申请号：US16553549

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Hiroki Fujisawa ,  Raj K. Bansal ,  Shunji Kuwahara ,  Mitsuaki Katagiri ,  Satoshi Isa

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  G11C11/4096

Abstract: Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.

公开(公告)号：US20210066247A1

公开(公告)日：2021-03-04

申请号：US16553549

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Hiroki Fujisawa ,  Raj K. Bansal ,  Shunji Kuwahara ,  Mitsuaki Katagiri ,  Satoshi Isa

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  G11C11/4096

Abstract: Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.

公开(公告)号：US20190013294A1

公开(公告)日：2019-01-10

申请号：US16056250

申请日：2018-08-06

Applicant: Micron Technology, Inc.

Inventor： Dai Sasaki ,  Mitsuaki Katagiri ,  Satoshi Isa

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L22/32 ,  H01L23/525 ,  H01L23/528 ,  H01L24/06 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06138 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: Some embodiments include an apparatus having a first chip and a second chip. Each of the first and second chips comprises a multilevel wiring structure and a redistribution wiring layer over the multilevel wiring structure. The redistribution wiring layers include redistribution wiring and pads electrically coupled to the redistribution wiring. The first chip is mounted above the second chip so that the redistribution wiring layer of the first chip faces the redistribution wiring layer of the second chip. The pad of the first chip faces the pad of the second chip, and is vertically spaced from the pad of the second chip by an intervening insulative region. The redistribution wiring of the second chip is electrically coupled to the redistribution wiring of the first chip through a bonding region.

公开(公告)号：US10600762B2

公开(公告)日：2020-03-24

申请号：US16447749

申请日：2019-06-20

Applicant: Micron Technology, Inc.

Inventor： Dai Sasaki ,  Mitsuaki Katagiri ,  Satoshi Isa

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/00 ,  H01L21/66 ,  H01L23/525

Abstract: Some embodiments include an apparatus having a first chip and a second chip. Each of the first and second chips comprises a multilevel wiring structure and a redistribution wiring layer over the multilevel wiring structure. The redistribution wiring layers include redistribution wiring and pads electrically coupled to the redistribution wiring. The first chip is mounted above the second chip so that the redistribution wiring layer of the first chip faces the redistribution wiring layer of the second chip. The pad of the first chip faces the pad of the second chip, and is vertically spaced from the pad of the second chip by an intervening insulative region. The redistribution wiring of the second chip is electrically coupled to the redistribution wiring of the first chip through a bonding region.

公开(公告)号：US10115709B1

公开(公告)日：2018-10-30

申请号：US15644383

申请日：2017-07-07

Applicant: Micron Technology, Inc.

Inventor： Dai Sasaki ,  Mitsuaki Katagiri ,  Satoshi Isa

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/00 ,  H01L21/66

Abstract: Some embodiments include an apparatus having a first chip and a second chip. Each of the first and second chips comprises a multilevel wiring structure and a redistribution wiring layer over the multilevel wiring structure. The redistribution wiring layers include redistribution wiring and pads electrically coupled to the redistribution wiring. The first chip is mounted above the second chip so that the redistribution wiring layer of the first chip faces the redistribution wiring layer of the second chip. The pad of the first chip faces the pad of the second chip, and is vertically spaced from the pad of the second chip by an intervening insulative region. The redistribution wiring of the second chip is electrically coupled to the redistribution wiring of the first chip through a bonding region.

公开(公告)号：US11705432B2

公开(公告)日：2023-07-18

申请号：US17365741

申请日：2021-07-01

Applicant: Micron Technology, Inc.

Inventor： Hiroki Fujisawa ,  Raj K. Bansal ,  Shunji Kuwahara ,  Mitsuaki Katagiri ,  Satoshi Isa

IPC: G11C5/04 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  G11C11/4096 ,  H01L25/18

CPC classification number: H01L25/0657 ,  G11C11/4096 ,  H01L24/07 ,  H01L24/16 ,  H01L24/48 ,  H01L25/50 ,  H01L25/18 ,  H01L2224/0233 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06565

Abstract: Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.

公开(公告)号：US20210327856A1

公开(公告)日：2021-10-21

申请号：US17365741

申请日：2021-07-01

Applicant: Micron Technology, Inc.

Inventor： Hiroki Fujisawa ,  Raj K. Bansal ,  Shunji Kuwahara ,  Mitsuaki Katagiri ,  Satoshi Isa

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  G11C11/4096

Abstract: Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.