- 专利标题: Modular periphery tile for integrated circuit device
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申请号: US17392218申请日: 2021-08-02
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公开(公告)号: US11714941B2公开(公告)日: 2023-08-01
- 发明人: Chee Hak Teh , Ankireddy Nalamalpu , Md Altaf Hossain , Dheeraj Subbareddy , Sean R. Atsatt , Lai Guan Tang
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Fletcher Yoder, P.C.
- 分案原申请号: US16235933 2018.12.28
- 主分类号: G06F30/34
- IPC分类号: G06F30/34 ; H03K19/17736 ; H04L12/43 ; G06F15/78 ; H03K19/17796
摘要:
Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
公开/授权文献
- US20220198115A1 MODULAR PERIPHERY TILE FOR INTEGRATED CIRCUIT DEVICE 公开/授权日:2022-06-23
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