公开(公告)号：US11915996B2

公开(公告)日：2024-02-27

申请号：US16407587

申请日：2019-05-09

申请人： Intel Corporation

发明人： Robert Sankman ,  Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

IPC分类号： H01L23/427 ,  H01L23/31 ,  H01L23/367 ,  H01L23/433 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L23/427 ,  H01L23/3157 ,  H01L23/367 ,  H01L23/433 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5387 ,  H01L23/5389 ,  H01L25/0652 ,  H01L24/16 ,  H01L2224/16225

摘要： An integrated circuit structure that includes a first integrated circuit package and a second integrated circuit package is described. The two packages can be stacked above, for example, a printed circuit board. The top package is inverted, such that a first die of that top package is facing a second die of the bottom package. A cooling arrangement is in a gap between the first and second integrated circuit packages, and is thermally coupled to the first and second die. The cooling arrangement is to transfer heat generated by a first die of the first integrated circuit package and a second die of the second integrated circuit package. In some cases, structures comprising electrically conductive material (e.g., metal) are encapsulated by a molding compound or insulator, and extend between a first substrate of the first integrated circuit package and a second substrate of the second integrated circuit package.

公开(公告)号：US20220334630A1

公开(公告)日：2022-10-20

申请号：US17849625

申请日：2022-06-25

申请人： Intel Corporation

发明人： Sreedhar Ravipalli ,  Mahesh Kumashikar ,  Md Altaf Hossain ,  Ankireddy Nalamalpu

IPC分类号： G06F1/324 ,  G06F1/3206

摘要： A circuit system includes an accelerator circuit and a compute circuit. The accelerator circuit generates a request in response to receiving packets of data. The accelerator circuit generates an indication of a low power state based on a reduced number of the packets of data being received. The compute circuit performs a processing operation for the accelerator circuit using the packets of data in response to receiving the request. The compute circuit comprises a power management circuit that decreases a supply voltage in the compute circuit and decreases a frequency of a clock signal in the compute circuit in response to the indication of the low power state from the accelerator circuit.

公开(公告)号：US11121109B2

公开(公告)日：2021-09-14

申请号：US16023846

申请日：2018-06-29

申请人： Intel Corporation

发明人： Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

IPC分类号： G06F13/38 ,  H01L23/00 ,  H01L25/065 ,  G06F13/42 ,  G06F13/14

摘要： An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.

公开(公告)号：US09268724B2

公开(公告)日：2016-02-23

申请号：US14182053

申请日：2014-02-17

申请人： INTEL CORPORATION

发明人： Md Altaf Hossain ,  Kevin J. Doran ,  Nagi Aboulenein

IPC分类号： G06F3/00 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22

CPC分类号： G06F13/1689 ,  G06F13/1684 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/22 ,  G11C2207/2281 ,  G11C2207/229 ,  Y02D10/14

摘要： Disclosed embodiments may include a circuit having a plurality of data terminals, no more than two pairs of differential data strobe terminals associated with the plurality of data terminals, and digital logic circuitry. The digital logic circuitry may be coupled to the data terminals and configured to use the no more than two pairs of differential data strobe terminals concurrently with the plurality of data terminals to transfer data. Other embodiments may be disclosed.

摘要翻译： 公开的实施例可以包括具有多个数据终端的电路，与多个数据终端相关联的不超过两对差分数据选通端子和数字逻辑电路。 数字逻辑电路可以耦合到数据终端，并被配置为与多个数据终端同时使用不超过两对差分数据选通端子来传送数据。 可以公开其他实施例。

公开(公告)号：US11901299B2

公开(公告)日：2024-02-13

申请号：US18079753

申请日：2022-12-12

申请人： Intel Corporation

发明人： Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Robert Sankman ,  Ravindranath V. Mahajan ,  Debendra Mallik ,  Ram S. Viswanath ,  Sandeep B. Sane ,  Sriram Srinivasan ,  Rajat Agarwal ,  Aravind Dasu ,  Scott Weber ,  Ravi Gutala

IPC分类号： H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48

CPC分类号： H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L25/18 ,  H01L23/481 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2924/381

摘要： Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

公开(公告)号：US20230342309A1

公开(公告)日：2023-10-26

申请号：US18216867

申请日：2023-06-30

申请人： Intel Corporation

发明人： Md Altaf Hossain ,  Lai Guan Tang ,  Mahesh Kumashikar ,  Ankireddy Nalamalpu

IPC分类号： G06F13/10 ,  H01L25/065 ,  H01L23/538

CPC分类号： G06F13/102 ,  H01L25/0655 ,  H01L25/0652 ,  H01L23/538 ,  H01L24/14

摘要： A circuit system includes a support device that has first and second conductors. The circuit system also includes first, second, and third integrated circuits that are coupled to the support device. The second integrated circuit includes a peripheral region. The peripheral region includes a third conductor coupled between the first and the second conductors. The circuit system is configured to transmit a signal from the first integrated circuit through the first conductor, the third conductor, and the second conductor to the third integrated circuit. The first and the third integrated circuits are positioned diagonally in the circuit system

公开(公告)号：US11714941B2

公开(公告)日：2023-08-01

申请号：US17392218

申请日：2021-08-02

申请人： Intel Corporation

发明人： Chee Hak Teh ,  Ankireddy Nalamalpu ,  Md Altaf Hossain ,  Dheeraj Subbareddy ,  Sean R. Atsatt ,  Lai Guan Tang

IPC分类号： G06F30/34 ,  H03K19/17736 ,  H04L12/43 ,  G06F15/78 ,  H03K19/17796

CPC分类号： G06F30/34 ,  G06F15/7825 ,  H03K19/17744 ,  H03K19/17796 ,  H04L12/43

摘要： Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

公开(公告)号：US20230018793A1

公开(公告)日：2023-01-19

申请号：US17950728

申请日：2022-09-22

申请人： Intel Corporation

发明人： Md Altaf Hossain ,  Mahesh Kumashikar ,  Ankireddy Nalamalpu ,  Sreedhar Ravipalli

IPC分类号： G06F30/327

摘要： A processing integrated circuit includes a processing core comprising hard logic circuits and a programmable interface circuit configurable to exchange signals between an external terminal of the processing integrated circuit and the hard logic circuits in the processing core.

公开(公告)号：US20220326676A1

公开(公告)日：2022-10-13

申请号：US17852859

申请日：2022-06-29

申请人： Intel Corporation

发明人： Sreedhar Ravipalli ,  Mahesh Kumashikar ,  Md Altaf Hossain ,  Ankireddy Nalamalpu

IPC分类号： G05B19/05 ,  G06F15/78

摘要： A circuit system includes a processing circuit, an accelerator circuit, and a buffer circuit that stores packets of data and that is coupled to the processing circuit and to the accelerator circuit. The buffer circuit functions as a crossbar circuit by allowing each of the accelerator circuit and the processing circuit to access at least one of the packets of data stored in the buffer circuit during access to another one of the packets of data stored in the buffer circuit.

公开(公告)号：US11983135B2

公开(公告)日：2024-05-14

申请号：US17033593

申请日：2020-09-25

申请人： Intel Corporation

发明人： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  Anshuman Thakur ,  Md Altaf Hossain ,  Mahesh Kumashikar ,  Kemal Aygün ,  Casey Thielen ,  Daniel Klowden ,  Sandeep B. Sane

IPC分类号： G06F13/42 ,  G06F30/30 ,  G06F30/347

CPC分类号： G06F13/4221 ,  G06F13/4282 ,  G06F30/30 ,  G06F30/347 ,  G06F2213/0026

摘要： Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.