Invention Grant
- Patent Title: Electroless metal-defined thin pad first level interconnects for lithographically defined vias
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Application No.: US17536711Application Date: 2021-11-29
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Publication No.: US11728258B2Publication Date: 2023-08-15
- Inventor: Aleksandar Aleksov , Veronica Strong , Kristof Darmawikarta , Arnab Sarkar
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- The original application number of the division: US16641219
- Main IPC: H05K1/02
- IPC: H05K1/02 ; H05K1/03 ; H05K1/09 ; H05K3/02 ; H05K3/06 ; H05K3/07 ; H05K3/10 ; H01L21/00 ; H01L21/48 ; H01L23/00 ; H01L23/48 ; H01L23/498 ; H05K1/11 ; H05K3/18

Abstract:
A package substrate, comprising a package comprising a substrate, the substrate comprising a dielectric layer, a via extending to a top surface of the dielectric layer; and a bond pad stack having a central axis and extending laterally from the via over the first layer. The bond pad stack is structurally integral with the via, wherein the bond pad stack comprises a first layer comprising a first metal disposed on the top of the via and extends laterally from the top of the via over the top surface of the dielectric layer adjacent to the via. The first layer is bonded to the top of the via and the dielectric layer, and a second layer is disposed over the first layer. A third layer is disposed over the second layer. The second layer comprises a second metal and the third layer comprises a third metal. The second layer and the third layer are electrically coupled to the via.
Public/Granted literature
- US20220084927A1 ELECTROLESS METAL-DEFINED THIN PAD FIRST LEVEL INTERCONNECTS FOR LITHOGRAPHICALLY DEFINED VIAS Public/Granted day:2022-03-17
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