- Patent Title: Power aware translation lookaside buffer invalidation optimization
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Application No.: US17654726Application Date: 2022-03-14
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Publication No.: US11741017B2Publication Date: 2023-08-29
- Inventor: Kutty Banerjee , Pratik Chandresh Shah , Tatsuya Iwamoto , David E. Roberts
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Blank Rome LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/1027

Abstract:
One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.
Public/Granted literature
- US20220269619A1 Power Aware Translation Lookaside Buffer Invalidation Optimization Public/Granted day:2022-08-25
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