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公开(公告)号：US20230077058A1
公开(公告)日：2023-03-09
申请号：US17468328
申请日：2021-09-07
Applicant: Apple Inc.
Inventor： Benjamin Bowman , Fergus W. MacGarry , Kutty Banerjee , Pratik Chandresh Shah
Abstract: Disclosed techniques relate to distributing graphics work based on priority. In some embodiments, circuitry implements a plurality of tracking slots for sets of graphics work. A set of graphics processor sub-units may each implement multiple distributed hardware slots. Control circuitry may attempt to assign a first set of graphics work having a first priority to a graphics processor sub-unit that is currently executing graphics work having an equal or higher priority than the first priority, where the first set of graphics work is from a first tracking slot. The control circuitry may, in response to a failure of the attempt, generate a signal to graphics software that indicates the failure, wherein the signal indicates the first tracking slot. Disclosed techniques may reduce or avoid problems relating to higher priority work being scheduled behind lower priority work.
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公开(公告)号：US20230075531A1
公开(公告)日：2023-03-09
申请号：US17468312
申请日：2021-09-07
Applicant: Apple Inc.
Inventor： Benjamin Bowman , Fergus W. MacGarry , Kutty Banerjee , Pratik Chandresh Shah
IPC: G06F9/48
Abstract: Disclosed techniques relate to circuitry configured to aggregate and report usage information in a distributed processor (e.g., a GPU). In some embodiments, graphics processor circuitry that includes at least first and second portions that are respectively configured to execute sets of graphics work. First utilization circuitry may track execution time for sets of graphics work on the first portion of the graphics processor circuitry and second utilization circuitry may track execution time for sets of graphics work on the second portion of the graphics processor circuitry. Command queue circuitry may store multiple different command queues. Control circuitry may access the first and second utilization circuitry and aggregate utilization data on a per-command-queue basis, where for a given command queue, the aggregated utilization data indicates respective utilization of the first and second portions of the graphics processor circuitry. The control circuitry may provide the aggregated per-command-queue utilization data in software-accessible registers.
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公开(公告)号：US20220269619A1
公开(公告)日：2022-08-25
申请号：US17654726
申请日：2022-03-14
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Pratik Chandresh Shah , Tatsuya Iwamoto , David E. Roberts
IPC: G06F12/1027
Abstract: One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.
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公开(公告)号：US10719970B2
公开(公告)日：2020-07-21
申请号：US15864833
申请日：2018-01-08
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Rohan Sanjeev Patil , Pratik Chandresh Shah , Gokhan Avkarogullari , Tatsuya Iwamoto
Abstract: One disclosed embodiment includes a method of scheduling graphics commands for processing. A plurality of micro-commands is generated based on one or more graphics commands obtained from a central processing unit. The dependency between the one or more graphics commands is then determined and an execution graph is generated based on the determined dependency. Each micro-command in the execution graph is connected by an edge to the other micro-commands that it depends on. A wait count is defined for each micro-command of the execution graph, where the wait count indicates the number of micro-commands that the each particular micro-command depends on. One or more micro-commands with a wait count of zero are transmitted to a ready queue for processing.
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公开(公告)号：US12039368B2
公开(公告)日：2024-07-16
申请号：US17468328
申请日：2021-09-07
Applicant: Apple Inc.
Inventor： Benjamin Bowman , Fergus W. MacGarry , Kutty Banerjee , Pratik Chandresh Shah
CPC classification number: G06F9/4881 , G06F9/4831 , G06F9/5011 , G06F9/5038 , G06F9/546 , G06T1/20
Abstract: Disclosed techniques relate to distributing graphics work based on priority. In some embodiments, circuitry implements a plurality of tracking slots for sets of graphics work. A set of graphics processor sub-units may each implement multiple distributed hardware slots. Control circuitry may attempt to assign a first set of graphics work having a first priority to a graphics processor sub-unit that is currently executing graphics work having an equal or higher priority than the first priority, where the first set of graphics work is from a first tracking slot. The control circuitry may, in response to a failure of the attempt, generate a signal to graphics software that indicates the failure, wherein the signal indicates the first tracking slot. Disclosed techniques may reduce or avoid problems relating to higher priority work being scheduled behind lower priority work.
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Patent Agency Ranking
公开(公告)号：US20200379920A1
公开(公告)日：2020-12-03
申请号：US16786231
申请日：2020-02-10
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Pratik Chandresh Shah , Tatsuya Iwamoto , David E. Roberts
IPC: G06F12/1027
Abstract: One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.
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公开(公告)号：US20190213776A1
公开(公告)日：2019-07-11
申请号：US15864833
申请日：2018-01-08
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Rohan Sanjeev Patil , Pratik Chandresh Shah , Gokhan Avkarogullari , Tatsuya Iwamoto
Abstract: One disclosed embodiment includes a method of scheduling graphics commands for processing. A plurality of micro-commands is generated based on one or more graphics commands obtained from a central processing unit. The dependency between the one or more graphics commands is then determined and an execution graph is generated based on the determined dependency. Each micro-command in the execution graph is connected by an edge to the other micro-commands that it depends on. A wait count is defined for each micro-command of the execution graph, where the wait count indicates the number of micro-commands that the each particular micro-command depends on. One or more micro-commands with a wait count of zero are transmitted to a ready queue for processing.
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公开(公告)号：US12265844B2
公开(公告)日：2025-04-01
申请号：US17468312
申请日：2021-09-07
Applicant: Apple Inc.
Inventor： Benjamin Bowman , Fergus W. MacGarry , Kutty Banerjee , Pratik Chandresh Shah
IPC: G06F9/48
Abstract: Disclosed techniques relate to circuitry configured to aggregate and report usage information in a distributed processor (e.g., a GPU). In some embodiments, graphics processor circuitry that includes at least first and second portions that are respectively configured to execute sets of graphics work. First utilization circuitry may track execution time for sets of graphics work on the first portion of the graphics processor circuitry and second utilization circuitry may track execution time for sets of graphics work on the second portion of the graphics processor circuitry. Command queue circuitry may store multiple different command queues. Control circuitry may access the first and second utilization circuitry and aggregate utilization data on a per-command-queue basis, where for a given command queue, the aggregated utilization data indicates respective utilization of the first and second portions of the graphics processor circuitry. The control circuitry may provide the aggregated per-command-queue utilization data in software-accessible registers.
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公开(公告)号：US20240273666A1
公开(公告)日：2024-08-15
申请号：US18450910
申请日：2023-08-16
Applicant: Apple Inc.
Inventor： Steven Fishwick , David A. Gotwalt , Pratik Chandresh Shah , Jackson Dsouza , Subodh Asthana , Jairaj Dave , Piotr A. Dittrich , David E. Roberts
CPC classification number: G06T1/20 , G06F9/485 , G06F9/4881
Abstract: Disclosed techniques relate to scheduling sets of graphics work using queues. In some embodiments, tracking circuitry implements entries for multiple tracking slots for a graphics processor. Queue access circuitry may access a data structure in memory that specifies multiple queues, where each queue enqueues control information for multiple sets of graphics work. Queue select circuitry may select sets of graphics work from the data structure based on one or more selection parameters and store control information for selected sets of graphics work in tracking slots of the tracking slot circuitry. Distribution circuitry may assign portions of respective sets of graphics work from the tracking slots to graphics processor circuitry for execution.
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公开(公告)号：US11741017B2
公开(公告)日：2023-08-29
申请号：US17654726
申请日：2022-03-14
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Pratik Chandresh Shah , Tatsuya Iwamoto , David E. Roberts
IPC: G06F12/00 , G06F12/1027
CPC classification number: G06F12/1027 , G06F2212/683
Abstract: One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.
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