-
公开(公告)号：US20200104180A1
公开(公告)日：2020-04-02
申请号：US16145573
申请日：2018-09-28
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Benjamin Bowman , Terence M. Potter , Tatsuya Iwamoto , Gokhan Avkarogullari
Abstract: In general, embodiments are disclosed for tracking and allocating graphics processor hardware resources. More particularly, a graphics hardware resource allocation system is able to generate a priority list for a plurality of data masters for graphics processor based on a comparison between a current utilizations for the data masters and a target utilizations for the data masters. The graphics hardware resource allocation system designate, based on the priority list, a first data master with a higher priority to submit work to the graphics processor compared to a second data master. The graphics hardware resource allocation system determines a stall counter value for the data master and generates a notification to pause work for the second data master based on the stall counter value.
-
公开(公告)号：US09747659B2
公开(公告)日：2017-08-29
申请号：US14851629
申请日：2015-09-11
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Eric O. Sunalp , Tatsuya Iwamoto
CPC classification number: G06T1/20 , G06F9/5044 , G06F9/505 , G06F2209/5021 , G06T2200/28
Abstract: Embodiments are directed toward systems and methods for scheduling resources of a graphics processing unit that determine, for a number of applications having commands to be issued to the GPU, a static priority level and a dynamic priority level of each application, work iteratively across static priority levels until a resource budget of the GPU is consumed, and starting with a highest static priority identify the applications in a present static priority level, assign a processing budget of the GPU to each of the applications in the present static priority level according to their dynamic priority levels, and admit to a queue commands from the applications in the present static priority level according to their processing budgets, and release the queue to the GPU.
-
公开(公告)号：US20200379920A1
公开(公告)日：2020-12-03
申请号：US16786231
申请日：2020-02-10
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Pratik Chandresh Shah , Tatsuya Iwamoto , David E. Roberts
IPC: G06F12/1027
Abstract: One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.
-
公开(公告)号：US10795730B2
公开(公告)日：2020-10-06
申请号：US16145573
申请日：2018-09-28
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Benjamin Bowman , Terence M. Potter , Tatsuya Iwamoto , Gokhan Avkarogullari
Abstract: In general, embodiments are disclosed for tracking and allocating graphics processor hardware resources. More particularly, a graphics hardware resource allocation system is able to generate a priority list for a plurality of data masters for graphics processor based on a comparison between a current utilizations for the data masters and a target utilizations for the data masters. The graphics hardware resource allocation system designate, based on the priority list, a first data master with a higher priority to submit work to the graphics processor compared to a second data master. The graphics hardware resource allocation system determines a stall counter value for the data master and generates a notification to pause work for the second data master based on the stall counter value.
-
公开(公告)号：US20190213776A1
公开(公告)日：2019-07-11
申请号：US15864833
申请日：2018-01-08
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Rohan Sanjeev Patil , Pratik Chandresh Shah , Gokhan Avkarogullari , Tatsuya Iwamoto
Abstract: One disclosed embodiment includes a method of scheduling graphics commands for processing. A plurality of micro-commands is generated based on one or more graphics commands obtained from a central processing unit. The dependency between the one or more graphics commands is then determined and an execution graph is generated based on the determined dependency. Each micro-command in the execution graph is connected by an edge to the other micro-commands that it depends on. A wait count is defined for each micro-command of the execution graph, where the wait count indicates the number of micro-commands that the each particular micro-command depends on. One or more micro-commands with a wait count of zero are transmitted to a ready queue for processing.
-
Patent Agency Ranking
公开(公告)号：US20190108037A1
公开(公告)日：2019-04-11
申请号：US15961086
申请日：2018-04-24
Applicant: Apple Inc.
Inventor： Rohan Sanjeev Patil , Gokhan Avkarogullari , Tatsuya Iwamoto
IPC: G06F9/4401 , G06F1/32 , G06T1/20 , G06F9/50 , G06T15/00
Abstract: One disclosed embodiment includes a method of graphics processing. The method includes receiving an indication to update a current frame on a display. A plurality of graphics command are determined to be associated with a next frame that replaces the current frame. A power-up command is generated based on the received indication, configured to cause GPU hardware to begin an initialization operation. The central processing unit processes the plurality of graphics command. Prior to completely process the plurality of graphics command, a power-up command is sent to a GPU firmware. The GPU firmware initializes the GPU hardware based on the power-up command. The processed plurality of graphics command is also transmitted to the GPU hardware. The GPU hardware executes the processed plurality of graphics command to render the next frame on the display.
-
公开(公告)号：US11741017B2
公开(公告)日：2023-08-29
申请号：US17654726
申请日：2022-03-14
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Pratik Chandresh Shah , Tatsuya Iwamoto , David E. Roberts
IPC: G06F12/00 , G06F12/1027
CPC classification number: G06F12/1027 , G06F2212/683
Abstract: One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.
-
8.发明授权公开(公告)号：US11275697B2
公开(公告)日：2022-03-15
申请号：US16786231
申请日：2020-02-10
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Pratik Chandresh Shah , Tatsuya Iwamoto , David E. Roberts
IPC: G06F12/1027
Abstract: One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.
-
公开(公告)号：US20170269666A1
公开(公告)日：2017-09-21
申请号：US15074780
申请日：2016-03-18
Applicant: Apple Inc.
Inventor： Rohan S. Patil , Tatsuya Iwamoto , Gokhan Avkarogullari
IPC: G06F1/32
CPC classification number: G06F1/324 , G06F1/3206 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: Techniques for managing components of a processing system are described. Illustrative components include graphics processing units (GPUs), central processing units (CPUs), communication fabrics, memory controllers, or peripheral control circuits. For one embodiment, a performance control logic/module obtains information associated with components of a system during performance of a task by the system. The logic/module can determine the need to adjust an operational performance of a first component based on the obtained information. The performance control logic/module can also evaluate the obtained information to determine that the operational performance of one or more second components of the system should be adjusted to satisfy the determined need (of the first component). Moreover, the logic/module can adjust a first clock signal affecting the operational performance of the first component and one or more second clock signals affecting the operational performance of the one or more second components.
-
公开(公告)号：US11243598B2
公开(公告)日：2022-02-08
申请号：US16426633
申请日：2019-05-30
Applicant: Apple Inc.
Inventor： Tatsuya Iwamoto , Jason P. Jane , Rohan Sanjeev Patil , Kutty Banerjee , Subodh Asthana , Kyle J. Haughey
IPC: G06F1/32 , G06F1/3234 , G06F1/3287 , G06T1/20 , G06F17/18 , G06F1/3228
Abstract: Systems, methods, and computer readable media to manage power for a graphics processor are described. When the power management component determines the graphics processor is idle when processing a current frame by the graphics processor, the power management component predicts an idle period for the graphics processor based on the work history. The power management component obtains a first latency value indicative of a power on time period and a second latency value indicative of a power off time period for a graphics processor component, such as graphics processor hardware. The power management component provides power instructions to transition the graphics processor component to the power off state based on a determination that a combined latency value of the first latency value and the second latency value is less than the idle period.
-
-
-
-
-
-
-
-
-
Search Results
19
records
(took 0.014 seconds)
