公开(公告)号：US20200379920A1

公开(公告)日：2020-12-03

申请号：US16786231

申请日：2020-02-10

Applicant: Apple Inc.

Inventor： Kutty Banerjee ,  Pratik Chandresh Shah ,  Tatsuya Iwamoto ,  David E. Roberts

IPC: G06F12/1027

Abstract: One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.

公开(公告)号：US20220269619A1

公开(公告)日：2022-08-25

申请号：US17654726

申请日：2022-03-14

Applicant: Apple Inc.

Inventor： Kutty Banerjee ,  Pratik Chandresh Shah ,  Tatsuya Iwamoto ,  David E. Roberts

IPC: G06F12/1027

Abstract: One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.

公开(公告)号：US20240273666A1

公开(公告)日：2024-08-15

申请号：US18450910

申请日：2023-08-16

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  David A. Gotwalt ,  Pratik Chandresh Shah ,  Jackson Dsouza ,  Subodh Asthana ,  Jairaj Dave ,  Piotr A. Dittrich ,  David E. Roberts

IPC: G06T1/20 ,  G06F9/48

CPC classification number: G06T1/20 ,  G06F9/485 ,  G06F9/4881

Abstract: Disclosed techniques relate to scheduling sets of graphics work using queues. In some embodiments, tracking circuitry implements entries for multiple tracking slots for a graphics processor. Queue access circuitry may access a data structure in memory that specifies multiple queues, where each queue enqueues control information for multiple sets of graphics work. Queue select circuitry may select sets of graphics work from the data structure based on one or more selection parameters and store control information for selected sets of graphics work in tracking slots of the tracking slot circuitry. Distribution circuitry may assign portions of respective sets of graphics work from the tracking slots to graphics processor circuitry for execution.

公开(公告)号：US11741017B2

公开(公告)日：2023-08-29

申请号：US17654726

申请日：2022-03-14

Applicant: Apple Inc.

Inventor： Kutty Banerjee ,  Pratik Chandresh Shah ,  Tatsuya Iwamoto ,  David E. Roberts

IPC: G06F12/00 ,  G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/683

Abstract: One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.

公开(公告)号：US11275697B2

公开(公告)日：2022-03-15

申请号：US16786231

申请日：2020-02-10

Applicant: Apple Inc.

Inventor： Kutty Banerjee ,  Pratik Chandresh Shah ,  Tatsuya Iwamoto ,  David E. Roberts

IPC: G06F12/1027

Abstract: One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.