- 专利标题： Method for fabricating a metal gate transistor with a stacked double sidewall spacer structure
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申请号： US16985242申请日： 2020-08-05
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公开(公告)号： US11742412B2公开(公告)日： 2023-08-29
- 发明人: Te-Chang Hsu , Chun-Chia Chen , Yao-Jhan Wang , Chun-Jen Huang
- 申请人： UNITED MICROELECTRONICS CORP.
- 申请人地址： TW Hsin-Chu
- 专利权人： UNITED MICROELECTRONICS CORP.
- 当前专利权人： UNITED MICROELECTRONICS CORP.
- 当前专利权人地址： TW Hsin-Chu
- 代理商 Winston Hsu
- 优先权： TW 6128223 2017.08.21
- 分案原申请号： US15710820 2017.09.20
- 主分类号： H01L29/66
- IPC分类号： H01L29/66 ; H01L29/78 ; H01L29/49 ; H01L21/768 ; H01L21/28 ; H01L21/8238 ; H01L29/08 ; H01L29/16 ; H01L29/24 ; H01L29/161
摘要：
A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.
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