- 专利标题： Coordination and increased utilization of graphics processors during inference
-
申请号： US17871781申请日： 2022-07-22
-
公开(公告)号： US11748841B2公开(公告)日： 2023-09-05
- 发明人: Abhishek R. Appu , Altug Koker , John C. Weast , Mike B. Macpherson , Linda L. Hurd , Sara S. Baghsorkhi , Justin E. Gottschlich , Prasoonkumar Surti , Chandrasekaran Sakthivel , Liwei Ma , Elmoustapha Ould-Ahmed-Vall , Kamal Sinha , Joydeep Ray , Balaji Vembu , Sanjeev Jahagirdar , Vasanth Ranganathan , Dukhwan Kim
- 申请人： Intel Corporation
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Jaffery Watson Mendonsa & Hamilton LLP
- 主分类号： G06T1/20
- IPC分类号： G06T1/20 ; G06N3/063 ; G06F9/46 ; G06N3/045 ; G06N3/08 ; G06N3/084 ; G06N3/044
摘要：
A mechanism is described for facilitating inference coordination and processing utilization for machine learning. A method of embodiments, as described herein, includes limiting execution of workloads for the respective contexts of a plurality of contexts to a specified subset of a plurality of processing resources of a processing system according to physical resource slices of the processing system that are associated with the respective contexts of the plurality of contexts.
公开/授权文献
信息查询
