公开(公告)号：US20240004829A1

公开(公告)日：2024-01-04

申请号：US18350902

申请日：2023-07-12

申请人： Intel Corporation

发明人： Altug Koker ,  Farshad Akhbari ,  Feng Chen ,  Dukhwan Kim ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Liwei Ma ,  Jeremy Bottleson ,  Eriko Nurvitadhi ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu

IPC分类号： G06F15/80 ,  G06F13/40 ,  G06T1/20 ,  G06F9/30 ,  G06F13/00 ,  G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045 ,  G06N3/048

CPC分类号： G06F15/8007 ,  G06F13/4027 ,  G06T1/20 ,  G06F9/3004 ,  G06F13/00 ,  G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045 ,  G06N3/048

摘要： An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

公开(公告)号：US11797837B2

公开(公告)日：2023-10-24

申请号：US15494971

申请日：2017-04-24

申请人： Intel Corporation

发明人： Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  John C. Weast ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Farshad Akhbari ,  Nadathur Rajagopalan Satish ,  Liwei Ma ,  Jeremy Bottleson ,  Eriko Nurvitadhi ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC分类号： G06N3/08 ,  G06N20/00 ,  G06N3/063 ,  G06N3/044 ,  G06N3/045 ,  G06N3/048

CPC分类号： G06N3/08 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N20/00 ,  G06N3/048

摘要： In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230334316A1

公开(公告)日：2023-10-19

申请号：US18314450

申请日：2023-05-09

申请人： Intel Corporation

发明人： Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  John C. Weast ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Farshad Akhbari ,  Nadathur Rajagopalan Satish ,  Liwei Ma ,  Jeremy Bottleson ,  Eriko Nurvitadhi ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC分类号： G06N3/08 ,  G06N20/00 ,  G06N3/063 ,  G06N3/044 ,  G06N3/045

CPC分类号： G06N3/08 ,  G06N20/00 ,  G06N3/063 ,  G06N3/044 ,  G06N3/045 ,  G06N3/048

摘要： Described herein is a graphics processor comprising a memory device and a graphics processing cluster coupled with the memory device. The graphics processing cluster includes a plurality of graphics multiprocessors interconnected via a data interconnect. A graphics multiprocessor includes circuitry configured to load a modular neural network including a plurality of subnetworks, each of the plurality of subnetworks trained to perform a computer vision operation on a separate subject.

公开(公告)号：US11748106B2

公开(公告)日：2023-09-05

申请号：US17683564

申请日：2022-03-01

申请人： Intel Corporation

发明人： Liwei Ma ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Eriko Nurvitadhi ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC分类号： G06F9/38

CPC分类号： G06F9/3832

摘要： A mechanism is described for facilitating fast data operations and for facilitating a finite state machine for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting input data to be used in computational tasks by a computation component of a processor including a graphics processor. The method may further include determining one or more frequently-used data values (FDVs) from the data, and pushing the one or more frequent data values to bypass the computational tasks.

公开(公告)号：US20220382555A1

公开(公告)日：2022-12-01

申请号：US17839856

申请日：2022-06-14

申请人： Intel Corporation

发明人： ELMOUSTAPHA OULD-AHMED-VALL ,  BARATH LAKSHMANAN ,  TATIANA SHPEISMAN ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Ben J. Ashbaugh ,  Linda L. Hurd ,  Liwei Ma

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F13/42 ,  G06F13/40 ,  G06N20/00 ,  G06T1/20 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06N20/10 ,  G06F9/50 ,  G06F15/80 ,  G06N3/00

摘要： One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional floating-point operation, and the second instruction to cause the GPU to perform an integer operation; and a general-purpose graphics compute unit having a single instruction, multiple thread architecture, the general-purpose graphics compute unit to concurrently execute the first instruction and the second instruction.

公开(公告)号：US20210279571A1

公开(公告)日：2021-09-09

申请号：US17177632

申请日：2021-02-17

申请人： Intel Corporation

发明人： Narayan Srinivasa ,  Joydeep Ray ,  Nicolas C. Galoppo Von Borries ,  Ben J. Ashbaugh ,  Prasoonkumar Surti ,  Feng Chen ,  Barath Lakshmanan ,  Elmoustapha Ould-Ahmed-Vall ,  Liwei Ma ,  Linda L. Hurd ,  Abhishek R. Appu ,  John C. Weast ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Chandrasekaran Sakthivel ,  Farshad Akhbari ,  Dukhwan Kim ,  Altug Koker ,  Nadathur Rajagopalan Satish

IPC分类号： G06N3/08 ,  G06N3/04

摘要： An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.

公开(公告)号：US11010302B2

公开(公告)日：2021-05-18

申请号：US16326708

申请日：2016-10-05

申请人： INTEL CORPORATION

发明人： Liwei Ma ,  Jiqiang Song

IPC分类号： G06F12/0875 ,  G06N3/04 ,  G06N3/063 ,  G06T1/60 ,  B25J19/02 ,  G06N3/08 ,  G06F12/0802 ,  G06N3/00

摘要： A mechanism is described for facilitating general purpose input/output data capture and neutral cache system for autonomous machines. A method of embodiments, as described herein, includes capturing, by an image capturing device, one or more images of one or more objects, where the one or more images represent input data associated with a neural network. The method may further include determining accuracy of first output results generated by a default neural caching system by comparing the first output results with second output results predicted by a custom neural caching system. The method may further include outputting, based on the accuracy, a final output results including at least one of the first output results or the second output results.

公开(公告)号：US20190295211A1

公开(公告)日：2019-09-26

申请号：US16377315

申请日：2019-04-08

申请人： Intel Corporation

发明人： Abhishek R. Appu ,  Altug Koker ,  John C. Weast ,  Mike B. Macpherson ,  Linda L. Hurd ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Liwei Ma ,  Elmoustapha Ould-Ahmed-Vall ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan ,  Dukhwan Kim

IPC分类号： G06T1/20 ,  G06N3/08 ,  G06N3/063 ,  G06N3/04 ,  G06F9/46

摘要： A mechanism is described for facilitating inference coordination and processing utilization for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, at training time, information relating to one or more tasks to be performed according to a training dataset relating to a processor including a graphics processor. The method may further include analyzing the information to determine one or more portions of hardware relating to the processor capable of supporting the one or more tasks, and configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks.

公开(公告)号：US10409614B2

公开(公告)日：2019-09-10

申请号：US15494773

申请日：2017-04-24

申请人： Intel Corporation

发明人： Elmoustapha Ould-Ahmed-Vall ,  Barath Lakshmanan ,  Tatiana Shpeisman ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Ben J. Ashbaugh ,  Linda L. Hurd ,  Liwei Ma

IPC分类号： G06F9/38 ,  G06N3/00 ,  G06F15/80 ,  G06F9/50 ,  G06N3/08 ,  G06N3/063 ,  G06N3/04 ,  G06N20/00 ,  G06F9/30 ,  G06T1/20 ,  G06F13/42 ,  G06F13/40

摘要： One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising instruction decode logic to decode a single instruction including multiple operands into a single decoded instruction, the multiple operands having differing precisions and a general-purpose graphics compute unit including a first logic unit and a second logic unit, the general-purpose graphics compute unit to execute the single decoded instruction, wherein to execute the single decoded instruction includes to perform a first instruction operation on a first set of operands of the multiple operands at a first precision and a simultaneously perform second instruction operation on a second set of operands of the multiple operands at a second precision.

公开(公告)号：US10242423B2

公开(公告)日：2019-03-26

申请号：US15789565

申请日：2017-10-20

申请人： Intel Corporation

发明人： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC分类号： G06T1/20 ,  G06N99/00 ,  G06F7/483 ,  G06T15/00 ,  G06T1/60 ,  G06F3/14

摘要： One embodiment provides an accelerator module comprising a memory stack including multiple memory dies; a graphics processing unit (GPU) coupled with the memory stack via one or more memory controllers, the GPU including a plurality of multiprocessors having a single instruction, multiple thread (SIMT) architecture, the multiprocessors to execute at least one single instruction; the at least one single instruction to cause at least a portion of the GPU to perform a floating-point operation on input having differing precisions; and the floating-point operation is a two-dimensional matrix multiply and accumulate operation.