Invention Grant
- Patent Title: Thermally-optimized tunable stack in cavity package-on-package
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Application No.: US16051065Application Date: 2018-07-31
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Publication No.: US11769753B2Publication Date: 2023-09-26
- Inventor: George Vakanas , Aastha Uppal , Shereen Elhalawaty , Aaron McCann , Edvin Cetegen , Tannaz Harirchian , Saikumar Jayaraman
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Wlliamson & Wyatt, P.C.
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/373 ; H01L23/367 ; H01L23/00 ; H10B12/00

Abstract:
Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.
Public/Granted literature
- US20200043894A1 THERMALLY-OPTIMIZED TUNABLE STACK IN CAVITY PACKAGE-ON-PACKAGE Public/Granted day:2020-02-06
Information query
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