公开(公告)号：US12087731B2

公开(公告)日：2024-09-10

申请号：US18127539

申请日：2023-03-28

申请人： Intel Corporation

发明人： Wei Li ,  Edvin Cetegen ,  Nicholas S. Haehn ,  Ram S. Viswanath ,  Nicholas Neal ,  Mitul Modi

IPC分类号： H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L25/0652 ,  H01L21/486 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16225

摘要： Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

公开(公告)号：US12068222B2

公开(公告)日：2024-08-20

申请号：US17032577

申请日：2020-09-25

申请人： Intel Corporation

发明人： Mitul Modi ,  Joseph Van Nausdle ,  Omkar Karhade ,  Edvin Cetegen ,  Nicholas Haehn ,  Vaibhav Agrawal ,  Digvijay Raorane ,  Dingying Xu ,  Ziyin Lin ,  Yiqun Bai

IPC分类号： H01L23/42 ,  H01L21/48 ,  H01L23/31

CPC分类号： H01L23/42 ,  H01L21/481 ,  H01L23/3128

摘要： Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.

公开(公告)号：US11935861B2

公开(公告)日：2024-03-19

申请号：US16862287

申请日：2020-04-29

申请人： Intel Corporation

发明人： Frederick W. Atadana ,  Taylor William Gaines ,  Edvin Cetegen ,  Wei Li ,  Hsin-Yu Li ,  Tony Dambrauskas

IPC分类号： H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC分类号： H01L24/32 ,  H01L23/293 ,  H01L23/3157 ,  H01L24/29 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0675 ,  H01L2924/0715

摘要： Disclosed herein are structures and techniques for underfill flow management in electronic assemblies. For example, in some embodiments, an electronic assembly may include a first component, a second component, an underfill on the first component and at least partially between the first component and the second component, and a material at a surface of the first component, wherein the material is outside a footprint of the second component, and the underfill contacts the material with a contact angle greater than 50 degrees.

公开(公告)号：US20200273772A1

公开(公告)日：2020-08-27

申请号：US16287116

申请日：2019-02-27

申请人： Intel Corporation

发明人： Aastha Uppal ,  Omkar Karhade ,  Ram Viswanath ,  Je-Young Chang ,  Weihua Tang ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Kumar Singh

IPC分类号： H01L23/367 ,  H01L23/373 ,  H01L23/427 ,  H01L25/18 ,  H01L21/56

摘要： An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190279960A1

公开(公告)日：2019-09-12

申请号：US16349959

申请日：2016-12-14

申请人： Intel Corporation

发明人： Omkar G. Karhade ,  Edvin Cetegen ,  Sandeep B. Sane

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H05K1/18

摘要： Disclosed herein are integrated circuit (IC) packages with plates, as well as related devices and methods. For example, in some embodiments, an IC package may include: a package substrate; a plurality of electrical components secured to a face of the package substrate; and a plate secured to the plurality of electrical components with an adhesive such that the plurality of electrical components are between the plate and the package substrate.

公开(公告)号：US20180090411A1

公开(公告)日：2018-03-29

申请号：US15279222

申请日：2016-09-28

申请人： Intel Corporation

发明人： Edvin Cetegen ,  Omkar G. Karhade ,  Kedar Dhane ,  Chandra M. Jha

IPC分类号： H01L23/367 ,  H01L23/373

CPC分类号： H01L23/3736 ,  H01L23/3733 ,  H01L23/42 ,  H01L23/4275 ,  H01L23/433

摘要： A thermal interface may include a wired network made of a first TIM, and a second TIM surrounding the wired network. A heat spreader lid may include a wired network attached to an inner surface of the heat spreader lid. An IC package may include a heat spreader lid placed over a first electronic component and a second electronic component. A first thermal interface may be formed between the first electronic component and the inner surface of the heat spreader lid, and a second thermal interface may be formed between the second electronic component and the inner surface of the heat spreader lid. The first thermal interface may include a wired network of a first TIM surrounded by a second TIM, while the second thermal interface may include the second TIM, without a wired network of the first TIM. Other embodiments may be described and/or claimed.

公开(公告)号：US12009271B2

公开(公告)日：2024-06-11

申请号：US16511360

申请日：2019-07-15

申请人： Intel Corporation

发明人： Edvin Cetegen ,  Jacob Vehonsky ,  Nicholas S. Haehn ,  Thomas Heaton ,  Steve S. Cho ,  Rahul Jain ,  Tarek Ibrahim ,  Antariksh Rao Pratap Singh ,  Nicholas Neal ,  Sergio Chan Arguedas ,  Vipul Mehta

IPC分类号： H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/16 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/18161

摘要： Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

公开(公告)号：US11942393B2

公开(公告)日：2024-03-26

申请号：US16781563

申请日：2020-02-04

申请人： Intel Corporation

发明人： Wei Li ,  Edvin Cetegen ,  Nicholas S. Haehn ,  Mitul Modi ,  Nicholas Neal

IPC分类号： H01L23/373 ,  H01L23/00 ,  H01L23/367 ,  H01L23/522 ,  H01L23/538

CPC分类号： H01L23/3735 ,  H01L23/367 ,  H01L23/3736 ,  H01L24/16 ,  H01L24/81 ,  H01L23/5226 ,  H01L23/5384 ,  H01L2224/16225 ,  H01L2224/81203

摘要： Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder.

公开(公告)号：US11791274B2

公开(公告)日：2023-10-17

申请号：US16902777

申请日：2020-06-16

申请人： Intel Corporation

发明人： Manish Dubey ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Jinhe Liu ,  Sairam Agraharam ,  Mohit Bhatia ,  Edvin Cetegen

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L23/538 ,  H01L23/498

CPC分类号： H01L23/5389 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/1703

摘要： Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20220102242A1

公开(公告)日：2022-03-31

申请号：US17032577

申请日：2020-09-25

申请人： Intel Corporation

发明人： Mitul Modi ,  Joseph Van Nausdle ,  Omkar Karhade ,  Edvin Cetegen ,  Nicholas Haehn ,  Vaibhav Agrawal ,  Digvijay Raorane ,  Dingying Xu ,  Ziyin Lin ,  Yiqun Bai

IPC分类号： H01L23/42 ,  H01L23/31 ,  H01L21/48

摘要： Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.