公开(公告)号：US20210134698A1

公开(公告)日：2021-05-06

申请号：US16672858

申请日：2019-11-04

申请人： Intel Corporation

发明人： Kyle J. Arrington ,  Aaron McCann ,  Kelly Lofgreen ,  Elah Bozorg-Grayeli ,  Aravindha Antoniswamy ,  Joseph B. Petrini

IPC分类号： H01L23/373 ,  H01L23/00 ,  H01L25/00

摘要： A thermal interface structure may be formed comprising a thermally conductive substrate having a first surface and an opposing second surface, a first liquid metal layer on the first surface of the thermally conductive substrate, and a second liquid metal layer on the second surface of the thermally conductive substrate. The thermal interface structure may be used in an integrated circuit assembly or package between at least one integrated circuit device and a heat dissipation device.

公开(公告)号：US11769753B2

公开(公告)日：2023-09-26

申请号：US16051065

申请日：2018-07-31

申请人： Intel Corporation

发明人： George Vakanas ,  Aastha Uppal ,  Shereen Elhalawaty ,  Aaron McCann ,  Edvin Cetegen ,  Tannaz Harirchian ,  Saikumar Jayaraman

IPC分类号： H01L25/065 ,  H01L23/373 ,  H01L23/367 ,  H01L23/00 ,  H10B12/00

CPC分类号： H01L25/0657 ,  H01L23/367 ,  H01L23/3736 ,  H01L24/49 ,  H10B12/00

摘要： Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.

公开(公告)号：US11832419B2

公开(公告)日：2023-11-28

申请号：US16723865

申请日：2019-12-20

申请人： Intel Corporation

发明人： Nicholas Neal ,  Nicholas S. Haehn ,  Je-Young Chang ,  Kyle Arrington ,  Aaron McCann ,  Edvin Cetegen ,  Ravindranath V. Mahajan ,  Robert L. Sankman ,  Ken P. Hackenberg ,  Sergio A. Chan Arguedas

IPC分类号： H05K7/20 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367

CPC分类号： H05K7/20309 ,  H01L23/3672 ,  H01L23/49816 ,  H01L24/14

摘要： Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.

公开(公告)号：US11854935B2

公开(公告)日：2023-12-26

申请号：US16794789

申请日：2020-02-19

申请人： Intel Corporation

发明人： Weston Bertrand ,  Kyle Arrington ,  Shankar Devasenathipathy ,  Aaron McCann ,  Nicholas Neal ,  Zhimin Wan

IPC分类号： H01L23/433 ,  H01L25/065 ,  H01L23/367

CPC分类号： H01L23/433 ,  H01L23/3675 ,  H01L25/0657

摘要： Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US11679407B2

公开(公告)日：2023-06-20

申请号：US16913986

申请日：2020-06-26

申请人： Intel Corporation

发明人： Kyle Jordan Arrington ,  Joseph Blaine Petrini ,  Aaron McCann ,  Shankar Devasenathipathy ,  James Christopher Matayabas, Jr. ,  Mostafa Aghazadeh ,  Jerrod Peterson

IPC分类号： B05C1/02 ,  B05C1/00 ,  C23C28/00 ,  H05K7/20 ,  B05D1/28

CPC分类号： B05C1/02 ,  B05C1/00 ,  C23C28/00 ,  B05D1/28 ,  H05K7/2039

摘要： To address technical problems facing silicon transient thermal management, a thermal interface material (TIM) may be used to provide improved thermal conduction. The TIM may include a liquid metal (LM) TIM, which may provide a significant reduction in thermal resistance, such as a thermal resistance RTIM≈0.01-0.025° C.-cm2/W. The LM TIM may be applied using a presoaked applicator, such as an open-cell polyurethane foam applicator that has been presoaked in a controlled amount of LM TIM. This LM presoaked applicator is then used to apply the LM TIM to one or more target thermal surfaces, thereby providing thermal and mechanical coupling between the LM TIM and the thermal surface. The resulting thermal surface and thermally conductive LM TIM may be used to improve thermal conduction for various silicon-based devices, including various high-power, high-performance system-on-chip (SoC) packages, such as may be used in portable consumer products.

公开(公告)号：US12057369B2

公开(公告)日：2024-08-06

申请号：US18088478

申请日：2022-12-23

申请人： Intel Corporation

发明人： Weston Bertrand ,  Kyle Arrington ,  Shankar Devasenathipathy ,  Aaron McCann ,  Nicholas Neal ,  Zhimin Wan

IPC分类号： H01L23/433 ,  H01L23/367 ,  H01L25/065

CPC分类号： H01L23/433 ,  H01L23/3675 ,  H01L25/0657

摘要： Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US11869824B2

公开(公告)日：2024-01-09

申请号：US16672858

申请日：2019-11-04

申请人： Intel Corporation

发明人： Kyle J. Arrington ,  Aaron McCann ,  Kelly Lofgreen ,  Elah Bozorg-Grayeli ,  Aravindha Antoniswamy ,  Joseph B. Petrini

IPC分类号： H01L23/373 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L23/3735 ,  H01L23/3733 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/00 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32506 ,  H01L2224/73253

摘要： A thermal interface structure may be formed comprising a thermally conductive substrate having a first surface and an opposing second surface, a first liquid metal layer on the first surface of the thermally conductive substrate, and a second liquid metal layer on the second surface of the thermally conductive substrate. The thermal interface structure may be used in an integrated circuit assembly or package between at least one integrated circuit device and a heat dissipation device.