Invention Grant
- Patent Title: Integrated chip inductor structure
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Application No.: US16884319Application Date: 2020-05-27
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Publication No.: US11784211B2Publication Date: 2023-10-10
- Inventor: Hung-Wen Hsu , Po-Han Huang , Wei-Li Huang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01F7/06
- IPC: H01F7/06 ; H01L49/02 ; H01F27/02 ; H01F27/06 ; H01F27/36 ; H01F41/02 ; H01F41/10

Abstract:
The present disclosure relates to, in part, an inductor structure that includes an etch stop layer arranged over an interconnect structure overlying a substrate. A magnetic structure includes a plurality of stacked layers is arranged over the etch stop layer. The magnetic structure includes a bottommost layer that is wider than a topmost layer. A first conductive wire and a second conductive wire extend in parallel over the magnetic structure. The magnetic structure is configured to modify magnetic fields generated by the first and second conductive wires. A pattern enhancement layer is arranged between the bottommost layer of the magnetic structure and the etch stop layer. The pattern enhancement layer has a first thickness, and the bottommost layer of the magnetic structure has a second thickness that is less than the first thickness.
Public/Granted literature
- US20210376053A1 INTEGRATED CHIP INDUCTOR STRUCTURE Public/Granted day:2021-12-02
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