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公开(公告)号:US20230290809A1
公开(公告)日:2023-09-14
申请号:US17828844
申请日:2022-05-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Mei-Chi Lee , Chi-Cheng Chen , Wei-Li Huang , Kai Tzeng , Chun Yi Wu , Ming-Da Cheng
IPC: H01L49/02
CPC classification number: H01L28/10
Abstract: A method of forming a semiconductor device includes: forming a passivation layer over a conductive pad that is disposed over a substrate; and forming an inductive component over the passivation layer, including: forming a first insulation layer and a first magnetic layer successively over the passivation layer; forming a first polymer layer over the first magnetic layer; forming a first conductive feature over the first polymer layer; forming a second polymer layer over the first polymer layer and the first conductive feature; patterning the second polymer layer, where after the patterning, a first sidewall of the second polymer layer includes multiple segments, where an extension of a first segment of the multiple segments intersects the second polymer layer; and after patterning the second polymer layer, forming a second insulation layer and a second magnetic layer successively over the second polymer layer.
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公开(公告)号:US20210376053A1
公开(公告)日:2021-12-02
申请号:US16884319
申请日:2020-05-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Hung-Wen Hsu , Po-Han Huang , Wei-Li Huang
Abstract: The present disclosure relates to, in part, an inductor structure that includes an etch stop layer arranged over an interconnect structure overlying a substrate. A magnetic structure includes a plurality of stacked layers is arranged over the etch stop layer. The magnetic structure includes a bottommost layer that is wider than a topmost layer. A first conductive wire and a second conductive wire extend in parallel over the magnetic structure. The magnetic structure is configured to modify magnetic fields generated by the first and second conductive wires. A pattern enhancement layer is arranged between the bottommost layer of the magnetic structure and the etch stop layer. The pattern enhancement layer has a first thickness, and the bottommost layer of the magnetic structure has a second thickness that is less than the first thickness.
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公开(公告)号:US11094776B2
公开(公告)日:2021-08-17
申请号:US16432625
申请日:2019-06-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chi-Cheng Chen , Wei-Li Huang , Chun-Yi Wu , Kuang-Yi Wu , Hon-Lin Huang , Chih-Hung Su , Chin-Yu Ku , Chen-Shien Chen
IPC: H01L21/677 , H01L49/02 , H01F41/04 , H01L23/00 , H01L21/768 , H01L23/31 , H01L23/532
Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a passivation layer over a semiconductor substrate. The method also includes forming a magnetic element over the passivation layer. The method further includes forming an isolation layer over the magnetic element and the passivation layer. The isolation layer includes a polymer material. In addition, the method includes forming a conductive line over the isolation layer, and the conductive line extends across the magnetic element.
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公开(公告)号:US20190096804A1
公开(公告)日:2019-03-28
申请号:US16203632
申请日:2018-11-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Hon-Lin Huang , Chen-Shien Chen , Chin-Yu Ku , Kuan-Chih Huang , Wei-Li Huang
IPC: H01L23/522 , H01L21/768 , H01L49/02 , H01L23/31
CPC classification number: H01L23/5227 , H01L21/76832 , H01L23/3171 , H01L28/10 , H01L2224/11
Abstract: Semiconductor devices and methods of forming the same are provided. One of the semiconductor devices comprises a conductive layer, a first dielectric layer disposed over the conductive layer, a magnetic layer disposed over the first dielectric layer, and a plurality of tantalum layers and a plurality of tantalum oxide layers alternately disposed between the magnetic layer and the first dielectric layer.
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公开(公告)号:US11784211B2
公开(公告)日:2023-10-10
申请号:US16884319
申请日:2020-05-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Hung-Wen Hsu , Po-Han Huang , Wei-Li Huang
CPC classification number: H01L28/10 , H01F27/027 , H01F27/06 , H01F27/36 , H01F41/0206 , H01F41/10
Abstract: The present disclosure relates to, in part, an inductor structure that includes an etch stop layer arranged over an interconnect structure overlying a substrate. A magnetic structure includes a plurality of stacked layers is arranged over the etch stop layer. The magnetic structure includes a bottommost layer that is wider than a topmost layer. A first conductive wire and a second conductive wire extend in parallel over the magnetic structure. The magnetic structure is configured to modify magnetic fields generated by the first and second conductive wires. A pattern enhancement layer is arranged between the bottommost layer of the magnetic structure and the etch stop layer. The pattern enhancement layer has a first thickness, and the bottommost layer of the magnetic structure has a second thickness that is less than the first thickness.
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公开(公告)号:US10720487B2
公开(公告)日:2020-07-21
申请号:US16260439
申请日:2019-01-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chin-Yu Ku , Chi-Cheng Chen , Hon-Lin Huang , Wei-Li Huang , Chun-Yi Wu , Chen-Shien Chen
IPC: H01L49/02
Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming an etch stop layer over a semiconductor substrate and forming a magnetic element over the etch stop layer. The method also includes forming an isolation element extending across the magnetic element. The isolation element partially covers the top surface of the magnetic element and partially covers sidewall surfaces of the magnetic element. The method further includes forming a conductive line over the isolation element. In addition, the method includes forming a dielectric layer over the conductive line, the isolation element, and the magnetic element.
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公开(公告)号:US20180350739A1
公开(公告)日:2018-12-06
申请号:US15798422
申请日:2017-10-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Hon-Lin Huang , Chen-Shien Chen , Chin-Yu Ku , Kuan-Chih Huang , Wei-Li Huang
IPC: H01L23/522 , H01L49/02 , H01L21/768
CPC classification number: H01L23/5227 , H01L21/76832 , H01L23/3171 , H01L28/10
Abstract: Semiconductor devices and methods of forming the same are disclosed. One of the semiconductor devices includes a conductive layer, a first dielectric layer, a magnetic layer and an etch stop stack. The first dielectric layer is disposed over the conductive layer. The magnetic layer is disposed over the first dielectric layer. The etch stop stack is disposed between the magnetic layer and the first dielectric layer. The etch stop stack includes a second dielectric layer and a plurality of unit layers between the second dielectric layer and the magnetic layer, and each of the plurality of unit layers comprises a tantalum layer and a tantalum oxide layer on the tantalum layer.
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公开(公告)号:US11329124B2
公开(公告)日:2022-05-10
申请号:US16907699
申请日:2020-06-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chin-Yu Ku , Chi-Cheng Chen , Hon-Lin Huang , Wei-Li Huang , Chun-Yi Wu , Chen-Shien Chen
IPC: H01L49/02
Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The semiconductor device structure also includes an isolation element over the magnetic element. The isolation element partially covers a top surface of the magnetic element. The semiconductor device structure further includes a conductive line over the isolation element. In addition, the semiconductor device structure includes a dielectric layer over the conductive line and the magnetic element.
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公开(公告)号:US11233116B2
公开(公告)日:2022-01-25
申请号:US16933062
申请日:2020-07-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chi-Cheng Chen , Wei-Li Huang , Chien-Chih Kuo , Hon-Lin Huang , Chin-Yu Ku , Chen-Shien Chen
IPC: H01L49/02 , H01F41/04 , H01L23/00 , H01L21/768 , H01L23/31 , H01L23/532
Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The magnetic element has a first edge. The semiconductor device structure also includes an adhesive element between the magnetic element and the semiconductor substrate, and the adhesive element has a second edge. The semiconductor device structure further includes an isolation element extending across the magnetic element. The isolation element partially covers a top surface of the magnetic element and partially covers sidewall surfaces of the magnetic element. The isolation element has a third edge, and the second edge is closer to the third edge than the first edge. In addition, the semiconductor device structure includes a conductive line over the isolation element.
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公开(公告)号:US11171085B2
公开(公告)日:2021-11-09
申请号:US16222107
申请日:2018-12-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Hon-Lin Huang , Wei-Li Huang , Chun-Kai Tzeng , Cheng-Jen Lin , Chin-Yu Ku
IPC: H01L23/522 , H01L23/528 , H01L49/02 , H01L23/532
Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, and the substrate includes a first region and a second region. The semiconductor device structure includes a first conductive structure formed over the first region of the substrate and a bottom magnetic layer formed over the second region of the substrate. The semiconductor device structure also includes a second conductive structure formed over the bottom magnetic layer and a first insulating layer formed over a sidewall surface of the first conductive structure. The semiconductor device structure further includes a second insulating layer formed over the first insulating layer, and the second insulating layer has a stair-shaped structure.
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