SEMICONDUCTOR DEVICE WITH INDUCTIVE COMPONENT AND METHOD OF FORMING

    公开(公告)号:US20230290809A1

    公开(公告)日:2023-09-14

    申请号:US17828844

    申请日:2022-05-31

    CPC classification number: H01L28/10

    Abstract: A method of forming a semiconductor device includes: forming a passivation layer over a conductive pad that is disposed over a substrate; and forming an inductive component over the passivation layer, including: forming a first insulation layer and a first magnetic layer successively over the passivation layer; forming a first polymer layer over the first magnetic layer; forming a first conductive feature over the first polymer layer; forming a second polymer layer over the first polymer layer and the first conductive feature; patterning the second polymer layer, where after the patterning, a first sidewall of the second polymer layer includes multiple segments, where an extension of a first segment of the multiple segments intersects the second polymer layer; and after patterning the second polymer layer, forming a second insulation layer and a second magnetic layer successively over the second polymer layer.

    INTEGRATED CHIP INDUCTOR STRUCTURE

    公开(公告)号:US20210376053A1

    公开(公告)日:2021-12-02

    申请号:US16884319

    申请日:2020-05-27

    Abstract: The present disclosure relates to, in part, an inductor structure that includes an etch stop layer arranged over an interconnect structure overlying a substrate. A magnetic structure includes a plurality of stacked layers is arranged over the etch stop layer. The magnetic structure includes a bottommost layer that is wider than a topmost layer. A first conductive wire and a second conductive wire extend in parallel over the magnetic structure. The magnetic structure is configured to modify magnetic fields generated by the first and second conductive wires. A pattern enhancement layer is arranged between the bottommost layer of the magnetic structure and the etch stop layer. The pattern enhancement layer has a first thickness, and the bottommost layer of the magnetic structure has a second thickness that is less than the first thickness.

    Integrated chip inductor structure

    公开(公告)号:US11784211B2

    公开(公告)日:2023-10-10

    申请号:US16884319

    申请日:2020-05-27

    Abstract: The present disclosure relates to, in part, an inductor structure that includes an etch stop layer arranged over an interconnect structure overlying a substrate. A magnetic structure includes a plurality of stacked layers is arranged over the etch stop layer. The magnetic structure includes a bottommost layer that is wider than a topmost layer. A first conductive wire and a second conductive wire extend in parallel over the magnetic structure. The magnetic structure is configured to modify magnetic fields generated by the first and second conductive wires. A pattern enhancement layer is arranged between the bottommost layer of the magnetic structure and the etch stop layer. The pattern enhancement layer has a first thickness, and the bottommost layer of the magnetic structure has a second thickness that is less than the first thickness.

    Semiconductor device structure with magnetic element

    公开(公告)号:US11233116B2

    公开(公告)日:2022-01-25

    申请号:US16933062

    申请日:2020-07-20

    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The magnetic element has a first edge. The semiconductor device structure also includes an adhesive element between the magnetic element and the semiconductor substrate, and the adhesive element has a second edge. The semiconductor device structure further includes an isolation element extending across the magnetic element. The isolation element partially covers a top surface of the magnetic element and partially covers sidewall surfaces of the magnetic element. The isolation element has a third edge, and the second edge is closer to the third edge than the first edge. In addition, the semiconductor device structure includes a conductive line over the isolation element.

Patent Agency Ranking