Invention Grant
- Patent Title: Efficient and low latency memory access scheduling
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Application No.: US17490684Application Date: 2021-09-30
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Publication No.: US11789655B2Publication Date: 2023-10-17
- Inventor: Guanhao Shen , Ravindra Nath Bhargava
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Polansky & Associates, P.L.L.C.
- Agent Paul J. Polansky
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
A memory controller includes a command queue that receives and stores decoded memory commands and information related thereto including information indicating a type, a priority, an age, and a region of a memory system for a corresponding decoded memory command, and an arbiter coupled to the command queue and picks selected decoded memory commands among the decoded memory commands from the command queue for dispatch to the memory system by comparing the priority and the age for decoded memory commands having a first type. The arbiter detects when the command queue receives a decoded memory command of a second type opposite to said first type that accesses a first memory region of the memory system, and in response performs at least one pre-work action that reduces a latency of the decoded memory command of the second type.
Public/Granted literature
- US20220317934A1 EFFICIENT AND LOW LATENCY MEMORY ACCESS SCHEDULING Public/Granted day:2022-10-06
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