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    DRAM COMMAND STREAK MANAGEMENT
    2.
    发明申请
    DRAM COMMAND STREAK MANAGEMENT 有权

    公开(公告)号：US20210390071A1

    公开(公告)日：2021-12-16

    申请号：US16900632

    申请日：2020-06-12

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Guanhao Shen ,  Ravindra Nath Bhargava ,  Raghava Sravan Adidamu

    IPC: G06F13/40

    Abstract: A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. The arbiter has a current mode indicating the type of commands currently being transacted, and a cross mode indicating the other type. The arbiter is operable to monitor commands in the command queue for the current mode and the cross mode, and in response to designated conditions, send at least one cross-mode command to the memory interface queue while continuing to operate in the current mode. In response to an end streak condition, the arbiter swaps the current mode and the cross mode, and transacts the cross-mode command.

    DYNAMIC PAGE STATE AWARE SCHEDULING OF READ/WRITE BURST TRANSACTIONS
    3.
    发明申请
    DYNAMIC PAGE STATE AWARE SCHEDULING OF READ/WRITE BURST TRANSACTIONS 审中-公开

    公开(公告)号：US20190196995A1

    公开(公告)日：2019-06-27

    申请号：US15850751

    申请日：2017-12-21

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Guanhao Shen ,  Ravindra N. Bhargava ,  Kedarnath Balakrishnan

    IPC: G06F13/30 ,  G06F13/16 ,  G06F3/06

    CPC classification number: G06F13/30 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1626 ,  G06F13/1642

    Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory access requests have not been sent to the memory device in a current mode of a read mode and a write mode, a first cost corresponding to a latency associated with sending remaining requests in either the read queue or the write queue associated with the current mode is determined. If the first cost exceeds the cost of a data bus turnaround, the cost of a data bus turnaround comprising a latency incurred when switching a transmission direction of the data bus from one direction to an opposite direction, then a second cost is determined for sending remaining memory access requests to the memory device. If the second cost does not exceed the cost of the data bus turnaround, then a time for the data bus turnaround is indicated and the current mode of the memory controller is changed.

    Dynamic page state aware scheduling of read/write burst transactions
    4.
    发明授权
    Dynamic page state aware scheduling of read/write burst transactions 有权

    公开(公告)号：US12282439B2

    公开(公告)日：2025-04-22

    申请号：US17100254

    申请日：2020-11-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Guanhao Shen ,  Ravindra N. Bhargava ,  Kedarnath Balakrishnan

    IPC: G06F13/30 ,  G06F3/06 ,  G06F13/16

    Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory access requests have not been sent to the memory device in a current mode of a read mode and a write mode, a first cost corresponding to a latency associated with sending remaining requests in either the read queue or the write queue associated with the current mode is determined. If the first cost exceeds the cost of a data bus turnaround, the cost of a data bus turnaround comprising a latency incurred when switching a transmission direction of the data bus from one direction to an opposite direction, then a second cost is determined for sending remaining memory access requests to the memory device. If the second cost does not exceed the cost of the data bus turnaround, then a time for the data bus turnaround is indicated and the current mode of the memory controller is changed.

    Refresh management for memory
    6.
    发明授权
    Refresh management for memory 有权

    公开(公告)号：US11694739B2

    公开(公告)日：2023-07-04

    申请号：US17564575

    申请日：2021-12-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Kevin M. Brandl ,  Kedarnath Balakrishnan ,  Jing Wang ,  Guanhao Shen

    IPC: G11C11/406

    CPC classification number: G11C11/40615

    Abstract: A memory controller interfaces with a random access memory over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the memory. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.

    DYNAMIC PAGE STATE AWARE SCHEDULING OF READ/WRITE BURST TRANSACTIONS
    7.
    发明申请
    DYNAMIC PAGE STATE AWARE SCHEDULING OF READ/WRITE BURST TRANSACTIONS 有权

    公开(公告)号：US20210073152A1

    公开(公告)日：2021-03-11

    申请号：US17100254

    申请日：2020-11-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Guanhao Shen ,  Ravindra N. Bhargava ,  Kedarnath Balakrishnan

    IPC: G06F13/30 ,  G06F13/16 ,  G06F3/06

    Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory access requests have not been sent to the memory device in a current mode of a read mode and a write mode, a first cost corresponding to a latency associated with sending remaining requests in either the read queue or the write queue associated with the current mode is determined. If the first cost exceeds the cost of a data bus turnaround, the cost of a data bus turnaround comprising a latency incurred when switching a transmission direction of the data bus from one direction to an opposite direction, then a second cost is determined for sending remaining memory access requests to the memory device. If the second cost does not exceed the cost of the data bus turnaround, then a time for the data bus turnaround is indicated and the current mode of the memory controller is changed.

    Memory controller with flexible address decoding
    8.
    发明授权
    Memory controller with flexible address decoding 有权

    公开(公告)号：US10403333B2

    公开(公告)日：2019-09-03

    申请号：US15211887

    申请日：2016-07-15

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Kevin M. Brandl ,  Thomas Hamilton ,  Hideki Kanayama ,  Kedarnath Balakrishnan ,  James R. Magro ,  Guanhao Shen ,  Mark Fowler

    IPC: G11C7/10 ,  G06F12/1018 ,  G11C11/408

    Abstract: A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.

    Memory controller with hybrid DRAM/persistent memory channel arbitration
    10.
    发明授权
    Memory controller with hybrid DRAM/persistent memory channel arbitration 有权

    公开(公告)号：US11995008B2

    公开(公告)日：2024-05-28

    申请号：US17354806

    申请日：2021-06-22

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Guanhao Shen ,  Ravindra Nath Bhargava ,  James R. Magro ,  Kedarnath Balakrishnan

    IPC: G06F13/16 ,  G11C11/4063

    CPC classification number: G06F13/1642 ,  G11C11/4063

    Abstract: A memory controller includes a command queue having an input for receiving memory access commands for a memory channel, and a number of entries for holding a predetermined number of memory access commands, and an arbiter that selects memory commands from the command queue for dispatch to one of a persistent memory and a DRAM memory coupled to the memory channel. The arbiter includes a first-tier sub-arbiter circuit coupled to the command queue for selecting candidate commands from among DRAM commands and persistent memory commands, and a second-tier sub-arbiter circuit coupled to the first-tier sub-arbiter circuit for receiving the candidate commands and selecting at least one command from among the candidate commands.

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