公开(公告)号：US20210390071A1

公开(公告)日：2021-12-16

申请号：US16900632

申请日：2020-06-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava ,  Raghava Sravan Adidamu

IPC: G06F13/40

Abstract: A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. The arbiter has a current mode indicating the type of commands currently being transacted, and a cross mode indicating the other type. The arbiter is operable to monitor commands in the command queue for the current mode and the cross mode, and in response to designated conditions, send at least one cross-mode command to the memory interface queue while continuing to operate in the current mode. In response to an end streak condition, the arbiter swaps the current mode and the cross mode, and transacts the cross-mode command.

公开(公告)号：US20140129772A1

公开(公告)日：2014-05-08

申请号：US13669502

申请日：2012-11-06

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Kalamatianos ,  Ravindra Nath Bhargava ,  Ramkumar Jayaseelan

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0897

Abstract: A processor transfers prefetch requests from their targeted cache to another cache in a memory hierarchy based on a fullness of a miss address buffer (MAB) or based on confidence levels of the prefetch requests. Each cache in the memory hierarchy is assigned a number of slots at the MAB. In response to determining the fullness of the slots assigned to a cache is above a threshold when a prefetch request to the cache is received, the processor transfers the prefetch request to the next lower level cache in the memory hierarchy. In response, the data targeted by the access request is prefetched to the next lower level cache in the memory hierarchy, and is therefore available for subsequent provision to the cache. In addition, the processor can transfer a prefetch request to lower level caches based on a confidence level of a prefetch request.

Abstract translation: 处理器根据缺失地址缓冲区（MAB）的丰满度或基于预取请求的置信水平，将预取请求从目标缓存传输到存储器层次结构中的另一高速缓存。 内存层次结构中的每个高速缓存在MAB上分配了多个插槽。 响应于当接收到高速缓存的预取请求时，分配给高速缓存的时隙的丰满度高于阈值，则处理器将预取请求传送到存储器层级中的下一个较低级别的高速缓存。 作为响应，访问请求所针对的数据被预取到存储器层次结构中的下一个较低级缓存，因此可用于后续的缓存提供。 此外，处理器可以基于预取请求的置信水平将预取请求传送到较低级别的高速缓存。

公开(公告)号：US11995008B2

公开(公告)日：2024-05-28

申请号：US17354806

申请日：2021-06-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava ,  James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F13/16 ,  G11C11/4063

CPC classification number: G06F13/1642 ,  G11C11/4063

Abstract: A memory controller includes a command queue having an input for receiving memory access commands for a memory channel, and a number of entries for holding a predetermined number of memory access commands, and an arbiter that selects memory commands from the command queue for dispatch to one of a persistent memory and a DRAM memory coupled to the memory channel. The arbiter includes a first-tier sub-arbiter circuit coupled to the command queue for selecting candidate commands from among DRAM commands and persistent memory commands, and a second-tier sub-arbiter circuit coupled to the first-tier sub-arbiter circuit for receiving the candidate commands and selecting at least one command from among the candidate commands.

公开(公告)号：US20240069811A1

公开(公告)日：2024-02-29

申请号：US18243848

申请日：2023-09-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A data processing system includes a memory accessing agent for generating first memory access requests, a first memory system, and a first memory controller. The first memory system includes a first three-dimensional memory stack comprising a first plurality of stacked memory dice, wherein each memory die of the first three-dimensional memory stack includes a different logical rank of a first memory channel. The first memory controller picks second memory access requests from among the first memory access requests that access a given logical rank of the first memory channel, arbitrates between the second memory access requests, and generates memory access commands to the given logical rank in response to the arbitrating.

公开(公告)号：US20220413759A1

公开(公告)日：2022-12-29

申请号：US17357007

申请日：2021-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava

IPC: G06F3/06

Abstract: A data processor includes a staging buffer, a command queue, a picker, and an arbiter. The staging buffer receives and stores first memory access requests. The command queue stores second memory access requests, each indicating one of a plurality of ranks of a memory system. The picker picks among the first memory access requests in the staging buffer and provides selected ones of the first memory access requests to the command queue. The arbiter selects among the second memory access requests from the command queue based on at least a preference for accesses to a current rank of the memory system. The picker picks accesses to the current rank among the first memory access requests of the staging buffer and provides the selected ones of the first memory access requests to the command queue.

公开(公告)号：US11789655B2

公开(公告)日：2023-10-17

申请号：US17490684

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0673

Abstract: A memory controller includes a command queue that receives and stores decoded memory commands and information related thereto including information indicating a type, a priority, an age, and a region of a memory system for a corresponding decoded memory command, and an arbiter coupled to the command queue and picks selected decoded memory commands among the decoded memory commands from the command queue for dispatch to the memory system by comparing the priority and the age for decoded memory commands having a first type. The arbiter detects when the command queue receives a decoded memory command of a second type opposite to said first type that accesses a first memory region of the memory system, and in response performs at least one pre-work action that reduces a latency of the decoded memory command of the second type.

公开(公告)号：US11755246B2

公开(公告)日：2023-09-12

申请号：US17357007

申请日：2021-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A data processor includes a staging buffer, a command queue, a picker, and an arbiter. The staging buffer receives and stores first memory access requests. The command queue stores second memory access requests, each indicating one of a plurality of ranks of a memory system. The picker picks among the first memory access requests in the staging buffer and provides selected ones of the first memory access requests to the command queue. The arbiter selects among the second memory access requests from the command queue based on at least a preference for accesses to a current rank of the memory system. The picker picks accesses to the current rank among the first memory access requests of the staging buffer and provides the selected ones of the first memory access requests to the command queue.

公开(公告)号：US20220317928A1

公开(公告)日：2022-10-06

申请号：US17219535

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava

IPC: G06F3/06

Abstract: A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. The arbiter transacts a streak for at least a minimum burst length based on a number of commands of a designated type available to be selected by the arbiter. Following the minimum burst length, the arbiter decides to start a new streak of commands of a different type based on a first set of one or more conditions indicating intra-burst efficiency.

公开(公告)号：US20210357336A1

公开(公告)日：2021-11-18

申请号：US15931825

申请日：2020-05-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava ,  Raghava Sravan Adidamu

IPC: G06F13/16

Abstract: A memory controller an arbiter which causes streaks of read commands and streaks of write commands over the memory channel. During a streak, the arbiter monitors an indicator of data bus efficiency of the memory channel. Responsive to the indicator showing that data bus efficiency is less than a designated threshold, the arbiter stops the current streak and start a streak of the other type.

公开(公告)号：US11782640B2

公开(公告)日：2023-10-10

申请号：US17218703

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0653 ,  G06F3/0679

Abstract: A memory controller includes a command queue that receives and stores decoded memory commands and information related thereto including information indicating a type, a priority, an age, and a region of a memory system for a corresponding decoded memory command, and an arbiter coupled to the command queue and picks selected decoded memory commands among the decoded memory commands from the command queue for dispatch to the memory system by comparing the priority and the age for decoded memory commands having a first type. The arbiter detects when the command queue receives a decoded memory command of a second type opposite to said first type that accesses a first memory region of the memory system, and in response elevates at least one of the priority and the age of a decoded command of the first type that accesses the first memory region already stored in the command queue.