Invention Grant
- Patent Title: Pattern fidelity enhancement
-
Application No.: US17114070Application Date: 2020-12-07
-
Publication No.: US11791161B2Publication Date: 2023-10-17
- Inventor: Yu-Tien Shen , Ya-Wen Yeh , Wei-Liang Lin , Ya Hui Chang , Yung-Sung Yen , Wei-Hao Wu , Li-Te Lin , Ru-Gun Liu , Kuei-Shun Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: HAYNES AND BOONE, LLP
- The original application number of the division: US15689172 2017.08.29
- Main IPC: G03F7/09
- IPC: G03F7/09 ; H01L21/027 ; H01L21/033 ; H01L21/311 ; H01L21/306 ; G03F7/20 ; G03F7/11

Abstract:
The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate and a patterning layer over the substrate and forming a plurality of openings in the patterning layer. The substrate includes a plurality of features to receive a treatment process. The openings partially overlap with the features from a top view while a portion of the features remains covered by the patterning layer. Each of the openings is free of concave corners. The method further includes performing an opening expanding process to enlarge each of the openings and performing a treatment process to the features through the openings. After the opening expanding process, the openings fully overlap with the features from the top view.
Public/Granted literature
- US20210118674A1 Pattern Fidelity Enhancement Public/Granted day:2021-04-22
Information query
IPC分类: