- Patent Title: Semiconductor package including part of underfill on portion of a molding material surrounding sides of logic chip and memory stack on interposer and method for manufacturing the same
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Application No.: US17083932Application Date: 2020-10-29
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Publication No.: US11791282B2Publication Date: 2023-10-17
- Inventor: Jaekyung Yoo , Yeongkwon Ko , Jayeon Lee , Jaeeun Lee , Teakhoon Lee
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR 20200085061 2020.07.10
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/522 ; H01L23/00 ; H01L23/31 ; H01L23/495 ; H01L23/528 ; H01L23/532 ; H01L25/065 ; H01L25/18 ; H01L25/00 ; H01L21/48 ; H01L21/56 ; H01L23/498
Abstract:
A semiconductor package comprises a substrate; an interposer on the substrate; a first underfill between the substrate and the interposer; at least one logic chip and at least one memory stack on the interposer; and a molding material on the interposer while surrounding a side surface of the at least one logic chip and a side surface of the at least one memory stack. The molding material includes areas having different heights. The first underfill covers a portion of the molding material.
Public/Granted literature
- US20220013474A1 SEMICONDUCTOR PACKAGE INCLUDING UNDERFILL AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2022-01-13
Information query
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