公开(公告)号：US12237240B2

公开(公告)日：2025-02-25

申请号：US17573426

申请日：2022-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Park ,  Jongho Lee ,  Yeongkwon Ko ,  Teakhoon Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer to be spaced apart from each other, the semiconductor devices being electrically connected to the package substrate through the interposer, and a molding layer on the interposer covering the semiconductor devices and exposing upper surfaces of the semiconductor devices, the molding layer including at least one groove extending in one direction between the semiconductor devices, the groove having a predetermined depth from an upper surface of the molding layer.

公开(公告)号：US20250015025A1

公开(公告)日：2025-01-09

申请号：US18431869

申请日：2024-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyeong Heo ,  Sera Lee ,  Yeongkwon Ko

IPC: H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes a substrate, a dielectric structure disposed on the substrate, a via structure that penetrates the substrate and the dielectric structure, and a pad structure that is in contact with the via structure. The dielectric structure includes a first part and a second part disposed on the first part. The second part of the dielectric structure is disposed between the via structure and the pad structure. A top surface of the second part of the dielectric structure is coplanar with a top surface of the via structure.

公开(公告)号：US20240321667A1

公开(公告)日：2024-09-26

申请号：US18387682

申请日：2023-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghun Shin ,  Soyeon Kwon ,  Unbyoung Kang ,  Yeongkwon Ko

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/3185 ,  H01L21/568 ,  H01L21/78 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/06131 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/13014 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0665

Abstract: A semiconductor package includes a first semiconductor chip including a first surface and a second surface opposite to the first surface, a second semiconductor chip stacked on the first surface of the first semiconductor chip, and a molding layer contacting the first surface of the first semiconductor chip and a sidewall of the second semiconductor chip. The molding layer includes a first sidewall from a lower end of the first semiconductor chip to a first height in a first direction perpendicular to the first surface of the first semiconductor chip, a second sidewall from the first height to a second height in the first direction, and a flat surface that extends from the first height in a second direction that is parallel with the first surface of the first semiconductor chip.

公开(公告)号：US11923340B2

公开(公告)日：2024-03-05

申请号：US17405130

申请日：2021-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongkwon Ko ,  Jinwoo Park ,  Jaekyung Yoo ,  Teakhoon Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L23/295 ,  H01L23/3135 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/17 ,  H01L24/33 ,  H01L24/73 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/17181 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92143 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: A semiconductor package includes a package substrate on which a base chip is disposed. A first semiconductor chip is disposed on the base chip. A second semiconductor chip is disposed on the first semiconductor chip. An inner mold layer surrounds an upper surface of the base chip and respective side surfaces of the first semiconductor chip and the second semiconductor chip. A first outer mold layer is interposed between the package substrate and the base chip while covering at least a portion of a side surface of the base chip. A second outer mold layer is disposed on the first outer mold layer while covering at least a portion of a side surface of the inner mold layer. The second outer mold layer is spaced apart from the package substrate. The first outer mold layer and the second outer mold layer have different viscosities.

公开(公告)号：US20250079250A1

公开(公告)日：2025-03-06

申请号：US18810742

申请日：2024-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon Ko ,  Unbyoung Kang ,  Soyeon Kwon ,  Kuyoung Kim

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes a substrate structure, a plurality of semiconductor chips sequentially stacked on the substrate structure, a molding member on the substrate structure and surrounding side surfaces of the plurality of semiconductor chips, the molding member including a first material, and a first reforming portion in a side portion of the molding member, and extending horizontally in the side portion of the molding member to have a predetermined width from an outer side surface of the molding member. The first reforming portion may include a second material that is more brittle than the first material.

公开(公告)号：US11996367B2

公开(公告)日：2024-05-28

申请号：US18328322

申请日：2023-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongkwon Ko ,  Jaeeun Lee ,  Junyeong Heo

IPC: H01L23/538 ,  H01L25/065

CPC classification number: H01L23/5385 ,  H01L23/5386 ,  H01L25/0657

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, a plurality of semiconductor elements disposed on the first surface in a device region, an insulating protective layer, and a connection pad. The second surface is divided into a first region overlapping the device region, and a second region surrounding the first region. The insulating protective layer is disposed on the second surface of the semiconductor substrate, and includes an edge pattern positioned in the second region. The edge pattern includes a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate. The connection pad is disposed on the center portion of the insulating protective layer and is electrically connected to the semiconductor elements.

公开(公告)号：US11869821B2

公开(公告)日：2024-01-09

申请号：US17879272

申请日：2022-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon Ko ,  Seunghun Shin ,  Junyeong Heo

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L23/481 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541

Abstract: A semiconductor package includes: a first semiconductor chip including a first surface and a second surface opposite to each other and including first through electrodes; at least a second semiconductor chip stacked on the first surface of the first semiconductor chip and comprising second through electrodes electrically connected to the first through electrodes; and a molding layer contacting the first surface of the first semiconductor chip and a side wall of the at least one second semiconductor chip and including a first external side wall connected to and on the same plane as a side wall of the first semiconductor chip, wherein the first external side wall of the molding layer extends to be inclined with respect to a first direction orthogonal to the first surface of the first semiconductor chip, and both the external first side wall of the molding layer and the side wall of the first semiconductor chip have a first slope that is the same for both the first external side wall of the molding layer and the side wall of the first semiconductor chip.

公开(公告)号：US11791282B2

公开(公告)日：2023-10-17

申请号：US17083932

申请日：2020-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Yeongkwon Ko ,  Jayeon Lee ,  Jaeeun Lee ,  Teakhoon Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49833 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50

Abstract: A semiconductor package comprises a substrate; an interposer on the substrate; a first underfill between the substrate and the interposer; at least one logic chip and at least one memory stack on the interposer; and a molding material on the interposer while surrounding a side surface of the at least one logic chip and a side surface of the at least one memory stack. The molding material includes areas having different heights. The first underfill covers a portion of the molding material.

公开(公告)号：US11721669B2

公开(公告)日：2023-08-08

申请号：US16877169

申请日：2020-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyeong Heo ,  Jae-Eun Lee ,  Yeongkwon Ko ,  Donghoon Won

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3142 ,  H01L24/29 ,  H01L2224/94

Abstract: A semiconductor package is provided including a first semiconductor chip stack and a second semiconductor chip stack that are adjacent to each other. The first semiconductor chip stack includes a plurality of first semiconductor chips and a plurality of first adhesive layers. The second semiconductor chip stack includes a plurality of second semiconductor chips and a plurality of second adhesive layers. Each of the first semiconductor chips includes a first cell region and a first scribe lane that surrounds the first cell region. Each of the second semiconductor chips includes a second cell region and a second scribe lane that surrounds the second cell region. An area of the first scribe lane is greater than an area of the second scribe lane. The plurality of first adhesive layers and the plurality of second adhesive layers have the same coefficient of thermal expansion.

公开(公告)号：US20220319944A1

公开(公告)日：2022-10-06

申请号：US17573426

申请日：2022-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Park ,  Jongho Lee ,  Yeongkwon Ko ,  Teakhoon Lee

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498

Abstract: A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer to be spaced apart from each other, the semiconductor devices being electrically connected to the package substrate through the interposer, and a molding layer on the interposer covering the semiconductor devices and exposing upper surfaces of the semiconductor devices, the molding layer including at least one groove extending in one direction between the semiconductor devices, the groove having a predetermined depth from an upper surface of the molding layer.