公开(公告)号：US12237240B2

公开(公告)日：2025-02-25

申请号：US17573426

申请日：2022-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Park ,  Jongho Lee ,  Yeongkwon Ko ,  Teakhoon Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer to be spaced apart from each other, the semiconductor devices being electrically connected to the package substrate through the interposer, and a molding layer on the interposer covering the semiconductor devices and exposing upper surfaces of the semiconductor devices, the molding layer including at least one groove extending in one direction between the semiconductor devices, the groove having a predetermined depth from an upper surface of the molding layer.

公开(公告)号：US11923340B2

公开(公告)日：2024-03-05

申请号：US17405130

申请日：2021-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongkwon Ko ,  Jinwoo Park ,  Jaekyung Yoo ,  Teakhoon Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L23/295 ,  H01L23/3135 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/17 ,  H01L24/33 ,  H01L24/73 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/17181 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92143 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: A semiconductor package includes a package substrate on which a base chip is disposed. A first semiconductor chip is disposed on the base chip. A second semiconductor chip is disposed on the first semiconductor chip. An inner mold layer surrounds an upper surface of the base chip and respective side surfaces of the first semiconductor chip and the second semiconductor chip. A first outer mold layer is interposed between the package substrate and the base chip while covering at least a portion of a side surface of the base chip. A second outer mold layer is disposed on the first outer mold layer while covering at least a portion of a side surface of the inner mold layer. The second outer mold layer is spaced apart from the package substrate. The first outer mold layer and the second outer mold layer have different viscosities.

公开(公告)号：US11587906B2

公开(公告)日：2023-02-21

申请号：US17168238

申请日：2021-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Unbyoung Kang ,  Jongho Lee ,  Teakhoon Lee

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00

Abstract: A package structure includes a lower substrate, substrate connection terminals on the lower substrate, a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate, first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, as viewed in a plan view, and covering at least one of the substrate connection terminals, and a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in a plan view.

公开(公告)号：US11967581B2

公开(公告)日：2024-04-23

申请号：US18110446

申请日：2023-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Unbyoung Kang ,  Jongho Lee ,  Teakhoon Lee

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L25/0652 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/562 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A package structure includes a lower substrate, substrate connection terminals on the lower substrate, a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate, first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, as viewed in a plan view, and covering at least one of the substrate connection terminals, and a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in a plan view.

公开(公告)号：US11791282B2

公开(公告)日：2023-10-17

申请号：US17083932

申请日：2020-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Yeongkwon Ko ,  Jayeon Lee ,  Jaeeun Lee ,  Teakhoon Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49833 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50

Abstract: A semiconductor package comprises a substrate; an interposer on the substrate; a first underfill between the substrate and the interposer; at least one logic chip and at least one memory stack on the interposer; and a molding material on the interposer while surrounding a side surface of the at least one logic chip and a side surface of the at least one memory stack. The molding material includes areas having different heights. The first underfill covers a portion of the molding material.

公开(公告)号：US20220319944A1

公开(公告)日：2022-10-06

申请号：US17573426

申请日：2022-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Park ,  Jongho Lee ,  Yeongkwon Ko ,  Teakhoon Lee

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498

Abstract: A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer to be spaced apart from each other, the semiconductor devices being electrically connected to the package substrate through the interposer, and a molding layer on the interposer covering the semiconductor devices and exposing upper surfaces of the semiconductor devices, the molding layer including at least one groove extending in one direction between the semiconductor devices, the groove having a predetermined depth from an upper surface of the molding layer.

公开(公告)号：US20250167061A1

公开(公告)日：2025-05-22

申请号：US19029411

申请日：2025-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Park ,  Jongho Lee ,  Yeongkwon Ko ,  Teakhoon Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer to be spaced apart from each other, the semiconductor devices being electrically connected to the package substrate through the interposer, and a molding layer on the interposer covering the semiconductor devices and exposing upper surfaces of the semiconductor devices, the molding layer including at least one groove extending in one direction between the semiconductor devices, the groove having a predetermined depth from an upper surface of the molding layer.

公开(公告)号：US11462462B2

公开(公告)日：2022-10-04

申请号：US16787107

申请日：2020-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Jaeeun Lee ,  Yeongkwon Ko ,  Teakhoon Lee

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L25/18 ,  H01L21/48 ,  H01L25/00

Abstract: Semiconductor packages may include a semiconductor chip including a chip pad and a lower redistribution that includes a lower redistribution insulating layer and a lower redistribution pattern. The lower redistribution insulating layer may include a top surface facing the semiconductor chip. The semiconductor packages may also include a molding layer on a side of the semiconductor chip and including a bottom surface facing the lower redistribution structure and a conductive post in the molding layer. The conductive post may include a bottom surface contacting the lower redistribution. The top surface of the lower redistribution insulating layer may be closer to a top surface of the conductive post than a top surface of the molding layer. A roughness of the top surface of the molding layer may be greater than a roughness of the top surface of the conductive post.

公开(公告)号：US11362062B2

公开(公告)日：2022-06-14

申请号：US17142133

申请日：2021-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwan Hwang ,  Unbyoung Kang ,  Sangsick Park ,  Jihwan Suh ,  Soyoun Lee ,  Teakhoon Lee

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498

Abstract: A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion.

公开(公告)号：US20160086912A1

公开(公告)日：2016-03-24

申请号：US14721624

申请日：2015-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Teakhoon Lee

IPC: H01L23/00 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L24/83 ,  H01L21/4889 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/49827 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/14181 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2224/83

Abstract: A method for manufacturing a semiconductor package includes providing a first semiconductor chip having a first surface and a second surface opposing each other, the first semiconductor chip including through-electrodes extending between the first surface and the second surface, forming an adhesive layer on the first surface, providing the first semiconductor chip on a package substrate so that the adhesive layer contacts the package substrate, thermo-compressing the first semiconductor chip so that the adhesive layer protrudes from between the first semiconductor chip and the package substrate towards the outside of the first semiconductor chip to form a support part that covers sides of the first semiconductor chip, and providing a second semiconductor chip on the first semiconductor chip, the second semiconductor chip having a third surface and a fourth surface opposing each other, the second semiconductor chip including connection terminals formed on the third surface.

Abstract translation: 一种半导体封装的制造方法，其特征在于，具备：第一半导体芯片，具有相互相对的第一表面和第二表面，所述第一半导体芯片包括在所述第一表面和所述第二表面之间延伸的贯通电极， 在封装基板上提供第一半导体芯片，使得粘合层与封装基板接触，对第一半导体芯片进行热压缩，使得粘合剂层从第一半导体芯片和封装基板之间朝向第一半导体芯片的外部突出 半导体芯片以形成覆盖第一半导体芯片的侧面的支撑部分，并且在第一半导体芯片上提供第二半导体芯片，第二半导体芯片具有彼此相对的第三表面和第四表面，第二半导体芯片包括连接 终端形成在第三表面上。