公开(公告)号：US11923343B2

公开(公告)日：2024-03-05

申请号：US18059747

申请日：2022-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Jayeon Lee ,  Jae-eun Lee ,  Yeongkwon Ko ,  Jin-woo Park ,  Teak Hoon Lee

IPC: H01L25/065 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/3157 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

公开(公告)号：US11791282B2

公开(公告)日：2023-10-17

申请号：US17083932

申请日：2020-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Yeongkwon Ko ,  Jayeon Lee ,  Jaeeun Lee ,  Teakhoon Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49833 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50

Abstract: A semiconductor package comprises a substrate; an interposer on the substrate; a first underfill between the substrate and the interposer; at least one logic chip and at least one memory stack on the interposer; and a molding material on the interposer while surrounding a side surface of the at least one logic chip and a side surface of the at least one memory stack. The molding material includes areas having different heights. The first underfill covers a portion of the molding material.

公开(公告)号：US20240088092A1

公开(公告)日：2024-03-14

申请号：US18462610

申请日：2023-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Woohyeong Kim ,  Jinwoo Park ,  Jayeon Lee ,  Chungsun Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package includes a redistribution substrate having a first surface including first and a second regions and a second surface opposite to the first surface, and including a first redistribution layer, first and second semiconductor chips positioned in a first direction on the first region the redistribution substrate, each of the first and second semiconductor chips being electrically connected to the first redistribution layer, a first molding layer on the first region on the first and second semiconductor chips, a redistribution structure on the first molding layer and including a second redistribution layer, conductive posts on the first region and electrically connecting the first redistribution layer to the second redistribution layer, third and fourth semiconductor chips positioned in a second direction, intersecting the first direction, and each electrically connected to the second redistribution layer, and a second molding layer on the second region the redistribution substrate and on the third and fourth semiconductor chips.

公开(公告)号：US11538792B2

公开(公告)日：2022-12-27

申请号：US17140241

申请日：2021-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Jayeon Lee ,  Jae-eun Lee ,  Yeongkwon Ko ,  Jin-woo Park ,  Teak Hoon Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/13 ,  H01L23/498 ,  H01L25/00

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.