Invention Grant
- Patent Title: 3D semiconductor devices and structures
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Application No.: US18105041Application Date: 2023-02-02
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Publication No.: US11793005B2Publication Date: 2023-10-17
- Inventor: Deepak C. Sekar , Zvi Or-Bach
- Applicant: Monolithic 3D Inc.
- Applicant Address: US OR Klamath Falls
- Assignee: Monolithic 3D Inc.
- Current Assignee: Monolithic 3D Inc.
- Current Assignee Address: US OR Klamath Falls
- Agency: Patent PC PowerPatent
- Agent Bao Tran
- Main IPC: H10B63/00
- IPC: H10B63/00 ; H01L21/268 ; H01L21/683 ; H01L21/762 ; H01L21/822 ; H01L21/84 ; H01L27/06 ; H01L27/12 ; H01L29/78 ; H01L29/423 ; H10B10/00 ; H10B12/00 ; H10B41/20 ; H10B41/41 ; H10B43/20 ; H10B61/00 ; H01L27/105 ; H10B41/40 ; H10B43/40 ; H10N70/20 ; H10N70/00

Abstract:
A semiconductor device, the device comprising: a plurality of transistors, wherein at least one of said plurality of transistors comprises a first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a second single crystal source, channel, and drain, wherein said second single crystal source, channel, and drain is disposed above said first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a third single crystal source, channel, and drain, wherein said third single crystal source, channel, and drain is disposed above said second single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a fourth single crystal source, channel, and drain, and wherein said third single crystal channel is self-aligned to said fourth single crystal channel being processed following the same lithography step.
Public/Granted literature
- US20230189537A1 3D SEMICONDUCTOR DEVICES AND STRUCTURES Public/Granted day:2023-06-15
Information query