公开(公告)号：US20240349504A1

公开(公告)日：2024-10-17

申请号：US18527356

申请日：2023-12-03

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Jin-Woo Han

IPC分类号： H10B43/27 ,  H01L23/528 ,  H01L27/02 ,  H01L29/167 ,  H01L29/47 ,  H01L29/78 ,  H01L29/792 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B53/20

CPC分类号： H10B43/27 ,  H01L23/5283 ,  H01L27/0207 ,  H01L29/167 ,  H01L29/47 ,  H01L29/7827 ,  H01L29/792 ,  H10B43/10 ,  H10B43/20 ,  H10B41/10 ,  H10B41/20 ,  H10B53/20

摘要： A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and at least one power-down control circuit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.

公开(公告)号：US12119056B2

公开(公告)日：2024-10-15

申请号：US17701463

申请日：2022-03-22

申请人： Micron Technology, Inc.

发明人： Ferdinando Bedeschi

IPC分类号： G11C13/00 ,  G11C16/04 ,  H10B43/20

CPC分类号： G11C13/0026 ,  G11C13/0004 ,  G11C16/0483 ,  H10B43/20 ,  G11C2213/71

摘要： Methods, systems, and devices for multiple transistor architecture for three-dimensional memory arrays are described. A memory device may include conductive pillars coupled with an access line using two transistors positioned between the conductive pillar and the access line. As part of an access operation for a memory cell coupled with the conductive pillar, the memory device may be configured to bias the access line to a first voltage and activate the two transistors using a second voltage to couple the conductive pillar with the access line. Additionally, the memory device may be configured to bias a gate of a first transistor and a gate of a second transistor coupling an unselected conductive pillar with the access line to a third and fourth voltage, respectively, which may deactivate at least one of the first or second transistor during the access operation and isolate the unselected conductive pillar from the access line.

公开(公告)号：US20240315019A1

公开(公告)日：2024-09-19

申请号：US18671074

申请日：2024-05-22

申请人： Kioxia Corporation

发明人： Hideto TAKEKIDA ,  Yosuke MURAKAMI ,  Keisuke NAKATSUKA ,  Yefei HAN

IPC分类号： H10B43/10 ,  H10B43/20 ,  H10B43/50

CPC分类号： H10B43/10 ,  H10B43/20 ,  H10B43/50

摘要： A semiconductor storage device of an embodiment includes a first conductive layer, a second conductive layer, a first conductive pillar, a first semiconductor layer, and a first storage layer. The first conductive layer extends in a first direction. The second conductive layer is along the first conductive layer in a third direction intersecting the first direction. The second conductive layer extends in the first direction. The first conductive pillar penetrates the first conductive layer and the second conductive layer in the third direction. The first semiconductor layer is in contact with the first conductive layer and the second conductive layer. The first semiconductor layer faces the first conductive pillar in the first direction. The first storage layer is between the first semiconductor layer and the first conductive pillar.

公开(公告)号：US20240297257A1

公开(公告)日：2024-09-05

申请号：US18658367

申请日：2024-05-08

申请人： Micron Technology, Inc.

发明人： Manzar Siddik ,  Terry H. Kim

IPC分类号： H01L29/792 ,  G11C16/04 ,  H01L29/423 ,  H10B43/20 ,  H10B43/30

CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L29/4234 ,  H10B43/20 ,  H10B43/30

摘要： Some embodiments include a memory cell having charge-trapping-material between a semiconductor channel material and a gating region. The charge-trapping-material includes silicon, nitrogen and trap-enhancing-additive. The trap-enhancing-additive includes one or more of carbon, phosphorus, boron and metal. Some embodiments include an integrated assembly having a stack of alternating first and second levels. The first levels include conductive structures and the second levels are insulative. Channel-material-pillars extend through the stack. Charge-trapping-regions are along the channel-material-pillars and are between the channel-material-pillars and the conductive structures. The charge-trapping-regions include a charge-trapping-material which contains silicon, nitrogen and trap-enhancing-additive. The trap-enhancing-additive includes one or more of carbon, phosphorus, boron and metal.

公开(公告)号：US12069860B2

公开(公告)日：2024-08-20

申请号：US18110604

申请日：2023-02-16

申请人： SK hynix Inc.

发明人： Yoo Hyun Noh ,  Da Yung Byun

IPC分类号： H10B43/20 ,  H01L23/522 ,  H10B41/20 ,  H10B41/40 ,  H10B43/40

CPC分类号： H10B43/20 ,  H01L23/5226 ,  H10B41/20 ,  H10B41/40 ,  H10B43/40

摘要： A semiconductor device includes a stacked structure including a first region in which conductive layers and the insulating layers are stacked alternately with each other, and a second region in which sacrificial layers and the insulating layers are stacked alternately with each other, a first slit structure located at a boundary between the first region and the second region and including a first through portion passing through the stacked structure and first protrusions extending from a sidewall of the first through portion, a second slit structure located at the boundary and including a second through portion passing through the stacked structure and second protrusions extending from a sidewall of the second through portion and coupled to the first protrusions, a circuit located under the stacked structure, and a contact plug passing through the second region of the stacked structure and electrically connected to the circuit.

公开(公告)号：US12069858B2

公开(公告)日：2024-08-20

申请号：US18194258

申请日：2023-03-31

申请人： Samsung Electronics Co., Ltd.

发明人： Woosung Yang ,  Byungjin Lee ,  Bumkyu Kang ,  Dong-Sik Lee

IPC分类号： H10B41/20 ,  G11C7/18 ,  G11C16/08 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/46 ,  H10B41/48 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/40

CPC分类号： H10B41/46 ,  G11C7/18 ,  G11C16/08 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/20 ,  H10B41/48 ,  H10B43/10 ,  H10B43/20 ,  H10B43/40

摘要： A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

公开(公告)号：US12068187B2

公开(公告)日：2024-08-20

申请号：US18424790

申请日：2024-01-27

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H10B20/20

CPC分类号： H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

摘要： A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layer; a second metal layer overlaying the first metal layer; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors and one capacitor, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.

公开(公告)号：US20240276727A1

公开(公告)日：2024-08-15

申请号：US18644137

申请日：2024-04-24

申请人： SK hynix Inc.

发明人： Young Jin LEE

IPC分类号： H10B43/27 ,  H10B41/10 ,  H10B41/20 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20

CPC分类号： H10B43/27 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B41/27

摘要： The present disclosure may provide a semiconductor device having a stable structure and a low manufacturing degree of the difficulty. The device may include conductive layers and insulating layers which are alternately stacked; a plurality of pillars passing through the conductive layers and the insulating layers; and a plurality of deposition inhibiting patterns, each deposition inhibiting pattern being formed along a portion of an interface between a side-wall of each of the pillars and each of the conductive layers and along a portion of an interface between each of the insulating layers and each of the conductive layers.

公开(公告)号：US20240268120A1

公开(公告)日：2024-08-08

申请号：US18165958

申请日：2023-02-08

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Yung-Hsiang CHEN ,  Tao-Cheng LU ,  Yao-Wen CHANG

IPC分类号： H10B43/35 ,  H01L23/528 ,  H10B41/20 ,  H10B41/35 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40

CPC分类号： H10B43/35 ,  H01L23/5283 ,  H10B41/20 ,  H10B41/35 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40

摘要： A semiconductor structure is provided. The semiconductor structure includes a first substrate, a first circuit layer, a memory array structure, a bonding layer, a second circuit layer, and a second substrate. The first circuit layer is disposed on the first substrate. The memory array structure is disposed on the first circuit layer. The bonding layer is disposed on the memory array structure. The second circuit layer is disposed on the bonding layer. The second substrate is disposed on the second circuit layer.

公开(公告)号：US20240250024A1

公开(公告)日：2024-07-25

申请号：US18420074

申请日：2024-01-23

申请人： Micron Technology, Inc.

发明人： Surendranath C. Eruvuru ,  Lifang Xu

IPC分类号： H01L23/528 ,  G11C16/04 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

CPC分类号： H01L23/5283 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

摘要： A stairless electrical interconnect structure with contact pillars embedded within and collectively accessing each tier in a periodic material stack, e.g., to provide electrical connections to access lines associated with a three-dimensional memory array, is described. The contact pillars can be formed in a corresponding array of vertical contact pillar trenches etched into the material stack in two stages to create depths of the trenches that vary between columns by a fixed number of tiers and then offset the depths between rows.