Invention Grant
- Patent Title: Reducing power consumption of communication interfaces by clock frequency scaling and adaptive interleaving of polling
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Application No.: US17558200Application Date: 2021-12-21
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Publication No.: US11797075B2Publication Date: 2023-10-24
- Inventor: Sandeep Kumar , Suman Kumar , Deven Balani
- Applicant: Qualcomm Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: QUALCOMM Incorporated
- The original application number of the division: US16222381 2018.12.17
- Main IPC: G06F1/324
- IPC: G06F1/324 ; G06F1/3234 ; G06F13/16 ; G06F13/42 ; G06F13/372

Abstract:
Reducing power consumption of communication interfaces by clock frequency scaling and adaptive interleaving of polling is disclosed. In a first aspect, a control system controls transmission of a command via a serial interface at a higher clock frequency. After transmission, the control system and the interface are operated at a lower clock frequency to save power during command execution. In this aspect, a reduction in polling corresponds to the reduction in clock signal frequency. When the command is complete, the interface is operated at the higher frequency to send another command. In a second aspect, after the control system sends a command to the receiving device, polling is suspended and an execution time of the command is tracked. Polling begins when the tracked execution time almost equals an expected completion time. Both aspects disclosed above may be implemented to reduce power consumption in exchange for a small increase in latency.
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