- Patent Title: Method for generating patterning device pattern at patch boundary
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Application No.: US17418102Application Date: 2019-11-18
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Publication No.: US11797748B2Publication Date: 2023-10-24
- Inventor: Quan Zhang , Yong-Ju Cho , Zhangnan Zhu , Boyang Huang , Been-Der Chen
- Applicant: ASML NETHERLANDS B.V.
- Applicant Address: NL Veldhoven
- Assignee: ASML NETHERLANDS B.V.
- Current Assignee: ASML NETHERLANDS B.V.
- Current Assignee Address: NL Veldhoven
- Agency: Pillsbury Winthrop Shaw Pittman, LLP
- International Application: PCT/EP2019/081574 2019.11.18
- International Announcement: WO2020/135946A 2020.07.02
- Date entered country: 2021-06-24
- Main IPC: G06F30/30
- IPC: G06F30/30 ; G03F7/00 ; G06F30/398 ; G03F1/36 ; G03F1/70 ; G03F1/44 ; G06F119/18

Abstract:
A method for generating a mask pattern to be employed in a patterning process. The method including obtaining (i) a first feature patch including a first polygon portion of an initial mask pattern, and (ii) a second feature patch including a second polygon portion of the initial mask pattern; adjusting the second polygon portion at a patch boundary between the first feature patch and the second feature patch such that a difference between the first polygon portion and the second polygon portion at the patch boundary is reduced; and combining the first polygon portion and the adjusted second polygon portion at the patch boundary to form the mask pattern.
Public/Granted literature
- US20220100079A1 METHOD FOR GENERATING PATTERNING DEVICE PATTERN AT PATCH BOUNDARY Public/Granted day:2022-03-31
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