Invention Grant
- Patent Title: Method of forming semiconductor packages having through package vias
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Application No.: US17215079Application Date: 2021-03-29
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Publication No.: US11837550B2Publication Date: 2023-12-05
- Inventor: Chen-Hua Yu , Chung-Shi Liu , Chih-Wei Lin , Ming-Da Cheng
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/56 ; H01L23/498 ; H01L23/31 ; H01L25/10 ; H01L23/00 ; H01L21/60

Abstract:
A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.
Public/Granted literature
- US20210233854A1 Method of Forming Semiconductor Packages Having Through Package Vias Public/Granted day:2021-07-29
Information query
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