公开(公告)号：US20240383744A1

公开(公告)日：2024-11-21

申请号：US18785430

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhao-Yi Wang ,  Chin-Yu Ku ,  Wen-Hsiung Lu ,  Lung-Kai Mao ,  Ming-Da Cheng

IPC: B81C1/00 ,  B81B3/00 ,  H01L25/00 ,  H01L25/065

Abstract: A method includes bonding a supporting substrate to a semiconductor substrate of a wafer. A bonding layer is between, and is bonded to both of, the supporting substrate and the semiconductor substrate. A first etching process is performed to etch the supporting substrate and to form an opening, which penetrates through the supporting substrate and stops on the bonding layer. The opening has substantially straight edges. The bonding layer is then etched. A second etching process is performed to extend the opening down into the semiconductor substrate. A bottom portion of the opening is curved.

公开(公告)号：US20240379584A1

公开(公告)日：2024-11-14

申请号：US18780104

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Tseng ,  Yu-Feng Chen ,  Cheng Jen Lin ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Kuo-Ching Hsu ,  Hong-Seng Shue ,  Ming-Hong Cha ,  Chao-Yi Wang ,  Mirng-Ji Lii

IPC: H01L23/58 ,  H01L21/02 ,  H01L21/48 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

公开(公告)号：US20240250019A1

公开(公告)日：2024-07-25

申请号：US18598266

申请日：2024-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ming-Da Cheng ,  Yung-Han Chuang ,  Hsueh-Sheng Wang

IPC: H01L23/522 ,  H01L21/48 ,  H01L23/00 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/486 ,  H01L23/528 ,  H01L24/11 ,  H01L24/14

Abstract: Methods for forming dummy under-bump metallurgy structures and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under-bump metallurgy (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and being electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure being electrically isolated from the second redistribution line by the first passivation layer.

公开(公告)号：US12009345B2

公开(公告)日：2024-06-11

申请号：US18149509

申请日：2023-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Hui-Min Huang ,  Hsuan-Ting Kuo ,  Ming-Da Cheng

IPC: H01L23/02 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76804 ,  H01L21/7684 ,  H01L21/76883 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06586

Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.

公开(公告)号：US11978720B2

公开(公告)日：2024-05-07

申请号：US17347871

申请日：2021-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai Jun Zhan ,  Chin-Fu Kao ,  Kuang-Chun Lee ,  Ming-Da Cheng ,  Chen-Shien Chen

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/16 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/81024 ,  H01L2224/81193 ,  H01L2224/81203

Abstract: A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.

公开(公告)号：US11955460B2

公开(公告)日：2024-04-09

申请号：US17063251

申请日：2020-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Da Tsai ,  Meng-Tse Chen ,  Sheng-Feng Weng ,  Sheng-Hsiang Chiu ,  Wei-Hung Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/481 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2221/68368 ,  H01L2224/0237 ,  H01L2224/024 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/06 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/0715 ,  H01L2924/14 ,  H01L2924/18162 ,  H01L2924/19011 ,  H01L2924/19102 ,  H01L2924/3511

Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

公开(公告)号：US20240096647A1

公开(公告)日：2024-03-21

申请号：US18521284

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mirng-Ji Lii ,  Chen-Shien Chen ,  Lung-Kai Mao ,  Ming-Da Cheng ,  Wen-Hsiung Lu

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L21/4857 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5383 ,  H01L24/80 ,  H01L2224/80345 ,  H01L2224/80355

Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.

公开(公告)号：US20240017988A1

公开(公告)日：2024-01-18

申请号：US18365997

申请日：2023-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhao-Yi Wang ,  Chin-Yu Ku ,  Wen-Hsiung Lu ,  Lung-Kai Mao ,  Ming-Da Cheng

IPC: B81C1/00 ,  B81B3/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: B81C1/00158 ,  B81B3/0072 ,  H01L25/0655 ,  H01L25/50 ,  B81B2203/033 ,  B81C2201/013 ,  B81B2203/0127

Abstract: A method includes bonding a supporting substrate to a semiconductor substrate of a wafer. A bonding layer is between, and is bonded to both of, the supporting substrate and the semiconductor substrate. A first etching process is performed to etch the supporting substrate and to form an opening, which penetrates through the supporting substrate and stops on the bonding layer. The opening has substantially straight edges. The bonding layer is then etched. A second etching process is performed to extend the opening down into the semiconductor substrate. A bottom portion of the opening is curved.

公开(公告)号：US11862588B2

公开(公告)日：2024-01-02

申请号：US17323506

申请日：2021-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Shien Chen ,  Ting-Li Yang ,  Po-Hao Tsai ,  Chien-Chen Li ,  Ming-Da Cheng

IPC: H01L23/31 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/16 ,  H01L2224/0236 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/16225

Abstract: In an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line.

公开(公告)号：US11851321B2

公开(公告)日：2023-12-26

申请号：US17188933

申请日：2021-03-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ting-Li Yang ,  Kai-Di Wu ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Cheng Jen Lin ,  Chin Wei Kang

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0081 ,  B81C1/0069 ,  B81B2203/019 ,  B81B2203/0127 ,  B81B2203/0353 ,  B81B2207/015 ,  B81C2201/013 ,  B81C2201/0181 ,  B81C2203/032 ,  B81C2203/0735

Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate comprising electronic circuitry, a support substrate having a recess, a bonding layer disposed between the circuit substrate and the support substrate, through holes passing through the circuit substrate to the recess, a first conductive layer disposed on a front side of the circuit substrate, and a second conductive layer disposed on an inner wall of the recess. The first conductive layer extends into the through holes and the second conductive layer extends into the through holes and coupled to the first conductive layer.