Invention Grant
- Patent Title: Vertical architecture of thin film transistors
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Application No.: US16016381Application Date: 2018-06-22
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Publication No.: US11843054B2Publication Date: 2023-12-12
- Inventor: Van H. Le , Seung Hoon Sung , Benjamin Chu-Kung , Miriam Reshotko , Matthew Metz , Yih Wang , Gilbert Dewey , Jack Kavalieros , Tahir Ghani , Nazila Haratipour , Abhishek Sharma , Shriram Shivaraman
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L29/417 ; H01L29/423 ; H01L23/522 ; H01L29/66 ; H01L29/49 ; H10B12/00

Abstract:
Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.
Public/Granted literature
- US20190393356A1 VERTICAL ARCHITECTURE OF THIN FILM TRANSISTORS Public/Granted day:2019-12-26
Information query
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