公开(公告)号：US20220208770A1

公开(公告)日：2022-06-30

申请号：US17696945

申请日：2022-03-17

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek A. Sharma ,  Tahir Ghani ,  Allen B. Gardiner ,  Travis W. Lajoie ,  Pei-hua Wang ,  Chieh-Jen Ku ,  Bernhard Sell ,  Juan G. Alzate-Vinasco ,  Blake C. Lin

IPC: H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L27/12

Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.

公开(公告)号：US20220122983A1

公开(公告)日：2022-04-21

申请号：US17563983

申请日：2021-12-28

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek Sharma ,  Van Le

IPC: H01L27/108 ,  H01L29/786 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  H01L23/528 ,  H01L49/02 ,  H01L29/24 ,  H01L29/66 ,  G11C11/4074

Abstract: Memory devices in which a memory cell includes a thin film select transistor and a capacitor (1TFT-1C). A 2D array of metal-insulator-metal capacitors may be fabricated over an array of the TFTs. Adjacent memory cells coupled to a same bitline may employ a continuous stripe of thin film semiconductor material. An isolation transistor that is biased to remain off may provide electrical isolation between adjacent storage nodes of a bitline. Wordline resistance may be reduced with a wordline shunt fabricated in a metallization level and strapped to gate terminal traces of the TFTs at multiple points over a wordline length. The capacitor array may occupy a footprint over a substrate. The TFTs providing wordline and bitline access to the capacitors may reside substantially within the capacitor array footprint. Peripheral column and row circuitry may employ FETs fabricated over a substrate substantially within the capacitor array footprint.

公开(公告)号：US11296087B2

公开(公告)日：2022-04-05

申请号：US16473592

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Shriram Shivaraman ,  Yih Wang ,  Tahir Ghani ,  Jack T. Kavalieros

IPC: H01L29/417 ,  H01L29/49 ,  H01L27/108 ,  H01L29/45 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

公开(公告)号：US11183594B2

公开(公告)日：2021-11-23

申请号：US15938153

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Shriram Shivaraman ,  Benjamin Chu-Kung ,  Yih Wang ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/04 ,  H01L27/108 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L29/423 ,  H01L21/311

Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.

公开(公告)号：US11094358B2

公开(公告)日：2021-08-17

申请号：US16319239

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Ilya Karpov ,  Yih Wang ,  Fatih Hamzaoglu ,  James Clarke

IPC: H01L21/02 ,  G11C11/00 ,  G11C11/22 ,  G11C11/407 ,  H01L27/108 ,  H01L27/11514 ,  H01L27/11507 ,  G11C11/401

Abstract: An apparatus is described. The apparatus includes a semiconductor chip that includes logic circuitry, embedded dynamic random access memory (DRAM) cells and embedded ferroelectric random access memory (FeRAM) cells.

公开(公告)号：US20240055531A1

公开(公告)日：2024-02-15

申请号：US18494384

申请日：2023-10-25

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Shriram Shivaraman ,  Benjamin Chu-Kung ,  Yih Wang ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/04 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L29/423 ,  H10B12/00

CPC classification number: H01L29/78642 ,  H01L29/78648 ,  H01L29/0847 ,  H01L29/04 ,  H01L29/6675 ,  H01L29/78696 ,  H01L29/1037 ,  H01L21/02647 ,  H01L29/6656 ,  H01L29/42384 ,  H10B12/05 ,  H10B12/50 ,  H10B12/315 ,  H01L21/31116

Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.

公开(公告)号：US11758711B2

公开(公告)日：2023-09-12

申请号：US17696945

申请日：2022-03-17

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek A. Sharma ,  Tahir Ghani ,  Allen B. Gardiner ,  Travis W. Lajoie ,  Pei-Hua Wang ,  Chieh-Jen Ku ,  Bernhard Sell ,  Juan G. Alzate-Vinasco ,  Blake C. Lin

IPC: H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H10B12/00 ,  H01L27/06 ,  H01L27/12

CPC classification number: H10B12/315 ,  H01L23/528 ,  H01L23/5223 ,  H01L23/5226 ,  H01L27/0605 ,  H01L27/124 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/482 ,  H10B12/488 ,  H10B12/50

Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.

公开(公告)号：US11469268B2

公开(公告)日：2022-10-11

申请号：US16067803

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Yih Wang

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/06 ,  H01F41/34 ,  H01L23/528 ,  H01L43/04 ,  H01L43/14 ,  H01L43/12 ,  H01F10/32 ,  H01L21/8234 ,  H01L29/78

Abstract: Damascene-based approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including a metallization layer. The logic processor also includes a memory array including a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall effect electrode (2T-1MTJ SHE electrode) bit cells. The spin hall effect electrodes of the 2T-1MTJ SHE electrode bit cells are disposed in a lower dielectric layer laterally adjacent to the metallization layer of the logic region. The MTJs of the 2T-1MTJ SHE electrode bit cells are disposed in an upper dielectric layer laterally adjacent to the metallization layer of the logic region.

公开(公告)号：US11373999B2

公开(公告)日：2022-06-28

申请号：US16002723

申请日：2018-06-07

Applicant: Intel Corporation

Inventor： Yih Wang ,  Rishabh Mehandru ,  Mauro J. Kobrinsky ,  Tahir Ghani ,  Mark Bohr ,  Marni Nabors

IPC: H01L27/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: Described herein are apparatuses, methods, and systems associated with a deep trench via in a three-dimensional (3D) integrated circuit (IC). The 3D IC may include a logic layer having an array of logic transistors. The 3D IC may further include one or more front-side interconnects on a front side of the 3D IC and one or more back-side interconnects on a back side of the 3D IC. The deep trench may be in the logic layer to conductively couple a front-side interconnect to a back-side interconnect. The deep trench via may be formed in a diffusion region or gate region of a dummy transistor in the logic layer. Other embodiments may be described and claimed.

公开(公告)号：US11322504B2

公开(公告)日：2022-05-03

申请号：US16021019

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Uygar Avci ,  Daniel Morris ,  Seiyon Kim ,  Yih Wang ,  Ruth Brain ,  Ian Young

IPC: H01L27/11502 ,  H01L27/11 ,  H01L23/528 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L21/311

Abstract: Embodiments include a memory array and a method of forming the memory array. A memory array includes a first dielectric over first metal traces, where first metal traces extend along a first direction, second metal traces on the first dielectric, where second metal traces extend along a second direction perpendicular to the first direction, and third metal traces on the second dielectric, where third metal traces extend along the first direction. The memory array includes a ferroelectric capacitor positioned in a trench having sidewalls and bottom surface, where the trench has a depth defined from a top surface of first metal trace to the top surface of third metal trace. The memory array further includes an insulating sidewall, a first electrode, a ferroelectric, and a second electrode disposed in the trench, where the trench has a rectangular cylinder shape defined by the first, second, and third metal traces.