Invention Grant
- Patent Title: Integrated circuit with reference sub-system for testing and replacement
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Application No.: US17672588Application Date: 2022-02-15
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Publication No.: US11852676B2Publication Date: 2023-12-26
- Inventor: Carlo Caimi , Massimiliano Pesaturo , Stefano Antonio Mastrorosa , Alfredo Lorenzo Poli , Marco Della Seta
- Applicant: STMICROELECTRONICS S.R.L.
- Applicant Address: IT Agrate Brianza
- Assignee: STMICROELECTRONICS S.R.L.
- Current Assignee: STMICROELECTRONICS S.R.L.
- Current Assignee Address: IT Agrate Brianza
- Agency: Seed IP Law Group LLP
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R31/00 ; G01R31/317 ; G01R31/3187 ; G01R31/3185

Abstract:
An integrated circuit includes a sub-system and a reference sub-system. The reference sub-system is substantially identical to the sub-system but is non-operating by default. The integrated circuit includes a test circuit that obtains a parameter value of the sub-system and a reference parameter from the reference sub-system. The integrated circuit detects deterioration of the sub-system based on the parameter value and the reference parameter. The integrated circuit deactivates the sub-system and activates the reference sub-system responsive to detecting deterioration of the sub-system.
Public/Granted literature
- US20230258709A1 INTEGRATED CIRCUIT WITH RESILIENT SYSTEM Public/Granted day:2023-08-17
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