Invention Grant
- Patent Title: Block level design method for heterogeneous PG-structure cells
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Application No.: US18096906Application Date: 2023-01-13
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Publication No.: US11853678B2Publication Date: 2023-12-26
- Inventor: Yen-Hung Lin , Yuan-Te Hou , Chung-Hsing Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- The original application number of the division: US15723308 2017.10.03
- Main IPC: G06F30/30
- IPC: G06F30/30 ; G06F30/392 ; G06F30/39 ; G06F30/398 ; G06F119/06 ; G06F119/12
Abstract:
A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.
Public/Granted literature
- US20230153507A1 BLOCK LEVEL DESIGN METHOD FOR HETEROGENEOUS PG-STRUCTURE CELLS Public/Granted day:2023-05-18
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