A method of fabricating a carrier chip for distributing signals among circuit elements of a quantum computing device, includes: providing a multilayer wiring stack, the multilayer wiring stack comprising alternating layers of dielectric material and wiring; bonding a capping layer to the multilayer wiring stack, in which the capping layer includes a single crystal silicon dielectric layer; forming a via hole within the capping layer, in which the via hole extends to a first wiring layer of the multilayer wiring stack; forming an electrically conductive via within the via hole and electrically coupled to the first wiring layer; and forming a circuit element on a surface of the capping layer, in which the circuit element is directly electrically coupled to the electrically conductive via.