Invention Grant
- Patent Title: Etch profile control of interconnect structures
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Application No.: US17542609Application Date: 2021-12-06
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Publication No.: US11854873B2Publication Date: 2023-12-26
- Inventor: Yu Lun Ke , Yi-Wei Chiu , Hung Jui Chang , Yu-Wei Kuo
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- The original application number of the division: US15725972 2017.10.05
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/74 ; H01L21/48 ; H01L23/522 ; H01L23/532

Abstract:
A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
Public/Granted literature
- US20220093457A1 Etch Profile Control of Interconnect Structures Public/Granted day:2022-03-24
Information query
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