公开(公告)号：US20220093457A1

公开(公告)日：2022-03-24

申请号：US17542609

申请日：2021-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Allen Ke ,  Yi-Wei Chiu ,  Hung Jui Chang ,  Yu-Wei Kuo

IPC: H01L21/768 ,  H01L21/74 ,  H01L21/48 ,  H01L23/522 ,  H01L23/532

Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.

公开(公告)号：US10707123B2

公开(公告)日：2020-07-07

申请号：US15725972

申请日：2017-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Allen Ke ,  Yi-Wei Chiu ,  Hung Jui Chang ,  Yu-Wei Kuo

IPC: H01L21/768 ,  H01L21/74 ,  H01L21/48 ,  H01L23/522 ,  H01L23/532

Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.

公开(公告)号：US10566232B2

公开(公告)日：2020-02-18

申请号：US15653368

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Jhih Shen ,  Yi-Wei Chiu ,  Hung Jui Chang

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02 ,  H01L21/285

Abstract: Implementations of the present disclosure provide methods for preventing contact damage or oxidation after via/trench opening formation. In one example, the method includes forming an opening in a structure on the substrate to expose a portion of a surface of an electrically conductive feature, and bombarding a surface of a mask layer of the structure using energy species formed from a plasma to release reactive species from the mask layer, wherein the released reactive species form a barrier layer on the exposed surface of the electrically conductive feature.

公开(公告)号：US12300593B2

公开(公告)日：2025-05-13

申请号：US18360169

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Tsai ,  Yi-Wei Chiu ,  Hung Jui Chang ,  Li-Te Hsu

IPC: H01L21/768 ,  H01L23/498

Abstract: A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.

公开(公告)号：US20210257285A1

公开(公告)日：2021-08-19

申请号：US17306319

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Tsai ,  Yi-Wei Chiu ,  Hung Jui Chang ,  Li-Te Hsu

IPC: H01L23/498 ,  H01L21/768

Abstract: A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.

公开(公告)号：US11031279B2

公开(公告)日：2021-06-08

申请号：US15672123

申请日：2017-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kai Sun ,  Yi-Wei Chiu ,  Hung Jui Chang ,  Chia-Ching Tsai

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/423 ,  H01L21/28 ,  H01L29/51 ,  H01L21/311

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having reduced trench loading effect. The present disclosure provides a novel multi-layer cap film incorporating one or more oxygen-based layers for reducing trench loading effects in semiconductor devices. The multi-layer cap film can be made of a metal hard mask layer and one or more oxygen-based layers. The metal hard mask layer can be formed of titanium nitride (TiN). The oxygen-based layer can be formed of tetraethyl orthosilicate (TEOS).

公开(公告)号：US10529543B2

公开(公告)日：2020-01-07

申请号：US16038825

申请日：2018-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chi Lin ,  Yi-Wei Chiu ,  Hung Jui Chang ,  Chin-Hsing Lin ,  Yu Lun Ke

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/683 ,  H01L21/311

Abstract: The present disclosure describes an exemplary etch process in a reactor that includes a shower head and an electrostatic chuck configured to receive a radio frequency (RF) power. The shower head includes a top plate and a bottom plate with one or more gas channels that receive incoming gases. The method can include (i) rotating the top plate or the bottom plate of the shower head to a first position to allow a gas to flow through the shower head; (ii) performing a surface modification cycle that includes: applying a negative direct current (DC) bias voltage to the shower head, applying an RF power signal to the wafer chuck; and (iii) performing an etching cycle that includes: removing the negative DC bias voltage from the shower head and lowering the RF power signal applied to the wafer chuck.

公开(公告)号：US11854873B2

公开(公告)日：2023-12-26

申请号：US17542609

申请日：2021-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Lun Ke ,  Yi-Wei Chiu ,  Hung Jui Chang ,  Yu-Wei Kuo

IPC: H01L21/768 ,  H01L21/74 ,  H01L21/48 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/4828 ,  H01L21/743 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2224/05093

Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.

公开(公告)号：US11195750B2

公开(公告)日：2021-12-07

申请号：US16202816

申请日：2018-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Allen Ke ,  Yi-Wei Chiu ,  Hung Jui Chang ,  Yu-Wei Kuo

IPC: H01L21/768 ,  H01L21/74 ,  H01L21/48 ,  H01L23/522 ,  H01L23/532

Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.

公开(公告)号：US11810846B2

公开(公告)日：2023-11-07

申请号：US17306319

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Tsai ,  Yi-Wei Chiu ,  Hung Jui Chang ,  Li-Te Hsu

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/76816 ,  H01L21/76831

Abstract: A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.