Invention Grant
- Patent Title: Enhanced base die heat path using through-silicon vias
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Application No.: US16794789Application Date: 2020-02-19
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Publication No.: US11854935B2Publication Date: 2023-12-26
- Inventor: Weston Bertrand , Kyle Arrington , Shankar Devasenathipathy , Aaron McCann , Nicholas Neal , Zhimin Wan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L23/433
- IPC: H01L23/433 ; H01L25/065 ; H01L23/367

Abstract:
Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.
Public/Granted literature
- US20210257277A1 ENHANCED BASE DIE HEAT PATH USING THROUGH-SILICON VIAS Public/Granted day:2021-08-19
Information query
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