Invention Grant
- Patent Title: Method for improving control gate uniformity during manufacture of processors with embedded flash memory
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Application No.: US17374573Application Date: 2021-07-13
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Publication No.: US11856767B2Publication Date: 2023-12-26
- Inventor: Meng-Han Lin , Wei Cheng Wu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Seed IP Law Group LLP
- Main IPC: H10B41/30
- IPC: H10B41/30 ; H10B41/40

Abstract:
A method includes planarizing a protective layer over gate materials overlying a recessed region in a substrate. The planarizing includes forming a first planarized surface by planarizing a sacrificial layer over the protective layer, and forming a second planarized surface of the protective layer by etching the first planarized surface of the sacrificial layer at an even rate across the recessed region. An etch mask layer is formed over the second planarized surface, and control gate stacks are formed in the recessed region by etching the gate materials.
Public/Granted literature
- US20210343733A1 METHOD FOR IMPROVING CONTROL GATE UNIFORMITY DURING MANUFACTURE OF PROCESSORS WITH EMBEDDED FLASH MEMORY Public/Granted day:2021-11-04
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