The graphics processing unit (GPU) of a processing system transitions to a low-power state between frame rendering operations according to an inter-frame power off process, where GPU state information is stored on retention hardware. The retention hardware can include retention random access memory (RAM) or retention flip-flops. The retention hardware is operable in an active mode and a retention mode, where read/write operations are enabled at the retention hardware in the active mode and disabled in the retention mode, but data stored on the retention hardware is still retained in the retention mode. The retention hardware is placed in the retention state between frame rendering operations. The GPU transitions from its low-power state to its active state upon receiving an indication that a new frame is ready to be rendered and is restored using the GPU state information stored at the retention hardware.